Signal mapping problem between Verilog netlist and SPEF parasitics

[TEEkohl]

This issue has been discussed before, but I wonder if it has been entirely resolved yet.

I am observing signal mapping problems between Verilog netlist and SPEF parasitics for all hierarchical signals with additional bit index. Example:

SPEF syntax: i_tmr_top/inst_spi_inst_spi_shiftreg_shift_state_tmr_b[1]
Verilog syntax: \i_tmr_top/inst_spi_inst_spi_shiftreg_shift_state_tmr_b [1]

Beware of the space in front of the bit index in Verilog.

I am using STA version 2.7.0 which should be the most recent one.

[jjcherry56]

It looks legit but it would help if there was a small testcase that exactly duplicates the issue.

[TEEkohl]

Please unpack attached testcase and within the STA_testcase directory run
=> sta ./sta.tcl | tee sta.log
Both 6_final.* files have been generated by the same Openroad-flow-scripts run.

STA_testcase.tar.gz

[jjcherry56]

Technically the spef requires the divider to be escaped like this:

i_tmr_top/inst_spi_inst_spi_shiftreg_shift_state_tmr_b[1]

because it does not separate hierarchical names.
But it seems that a lot of spef writers do not adhere to the spec, and I have tried to add
tolerance for them.

[TEEkohl]

I have rebuilt OpenSTA and now the signal name mapping between the Verilog netlist and the SPEF parasitics works.
Only the version number given out by the -version option should be incremented to reflect the update.