Shared ANSI-style port declarations lose width information in completion

[ParaN3xus]

When multiple ports share a declaration in ANSI-style Verilog port lists, the width/type information is only applied to the first identifier.

Example:

module test (
    input        reset,
    output       io_vgaClk,
    output [7:0] io_vgaR,
    io_vgaG,
    io_vgaB,
    output       io_vgaBlankN,
    io_vgaHs,
    io_vgaVs,
    io_vgaSyncN
);
endmodule

Here, io_vgaR, io_vgaG, and io_vgaB should all be treated as output [7:0].

However, completion behavior suggests that only io_vgaR is recognized as 8-bit wide. For example, in:

test u_test (
    .io_vgaR(V|), // <--------
    .io_vgaG(V|)  // <--------
);

Completion for .io_vgaR(V|) correctly suggests VGA_R, VGA_G, and VGA_B. But completion for .io_vgaG(V|) only suggests 1-bit signals (VGA_BLANK_N, VGA_CLK, etc.), as if io_vgaG were scalar instead of [7:0].

[hongjr03]

Thanks!