Reproduction
Preparing a.v and vizsla.toml:
module top(
input wire clk,
input wire rst,
output reg x
);
always @(posedge clk) begin
x <= x + 1;
end
endmodule
Step 1: Click Run Qihe Analysis
We can see the diagnostics "top.x needs resetting".
Step 2: Add the reset logic for x and click Run Qihe Analysis again
We can still see the diagnostics "top.x needs resetting" (until we modify the source code)

Reproduction
Preparing
a.vandvizsla.toml:Step 1: Click
Run Qihe AnalysisWe can see the diagnostics "top.x needs resetting".
Step 2: Add the reset logic for
xand clickRun Qihe AnalysisagainWe can still see the diagnostics "top.x needs resetting" (until we modify the source code)