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Fix merge conflicts
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I think the alignment requirements for This also means we can probably remove those pesky nops from the other backends too 😅 |
Isn't that in your branch that is not integrated yet? |
Yes but my branch has a lot of other changes so maybe two wrongs made a right there. I'll do a small PoC from the |
Okay so.... the current user of the alignment thing is Will look around to see if there's an easy fix. EDIT: Looks like there's one :) |
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I removed the conflict and disalignment generation for RISC-V, it is still missing the double dispatch for the |
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Hmmm this broke ~120 tests though... |
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…e no senders either because they are artifacts from the time we used diy flag registers to hangle CogIR or additional RISC-V instructions. It uses out-of-line literals, using dependent. This also adds support for rewriting literals or their references. This part is mostly based on the ARMv8 backend. A placeholder abstract compiler class is added for future expansions and to support isAbstract Note: vector concretization and missing methods (even unused) are added to silence compilation errors of translated code. Note 2: Add alignment nop check, needed in expectedClosedPICPrototype: as an OutOfLineLiteralsManager may add nops between the closedPICEnd and the start of the literals dump
…on flag registers (e.g. RISC-V or MIPS). see noteFollowingConditionalBranch:.
…the ABI of Smalltalk argument and result registers for the RISC-V backend
…rameter set for SIMD or vector operation. Split the VMJitMethodTest tests into the base one (staying in the class) and vectorized ones in VMJitVectorMethodTest
…rs number 1 and 2. While this corresponds to general registers in x86, x64, ARMv5, ARMv8 and MIPS, RISC-V defines register number 1 as the link register, register number 2 as the stack pointer. For a more robust encoding, the mask is built starting from the cResultRegister as defined in the backend
…expects all conditional branches to be preceeded by an instruction from which it can extracts the operand to fuse them into one compare and branch instruction, the Stop IR inclusion was preventing this mechanism. The test is slightly modified to keep the original usage. The count number is not a 1-to-1 mapping on RISC-V and breaks the corresponding test. Using the machineCodeSize, the number of instruction is inferred and used as a count for the final test.
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Hello, this PR (finally 😅) proposes the RISC-V JIT port.
Description:
The two main added files are the
CogRiscV64Compilerand correspondingCogRiscVOutOfLineLiteralsCompiler, adding the support for instructions, concretizations, and rewriting necessary to the JIT compiler. Code in these two classes might be tagged withCLEANUP. If it is, it means it either was used in a previous attempt to emulate flag registers, or defines instructions that were not used in the end.Since RISC-V, like MIPS does not provide flag registers, it uses the same tricks as the MIPS backend in the
opensmalltalk-vm. To this end, every conditional branch is notified and uses its previous instruction to combine into a single compare-and-branch instruction as available on this architecture. You can see this in action in theCogRiscV64Compiler >> noteFollowingConditionalBranch:method.Changes in existing files:
CogAbstractInstructionandCogObjectRepresentationFor64BitSpur: Add support for different disalignment withnopsbetween thecheckEntryandnoCheckEntry.Cogit: Add support for conditional branch notifications inFPjumpsVMSimpleStackBasedCogitAbstractTest: Addriscv64as a parameter for tests, redefined another category to hold SIMD/vector operations namedwordSize64SIMDParametersVMJitSimdBytecode,VMJitMethodTest,VMJitVectorMethodTest: Addword64SIMDParametersto the corresponding SIMD tests, splitJitMethodinto vectorized and non-vectorized testsUnicorn: Add support for RISC-V registers, redefine the ABI correctly on RISC-V sideVMTrampolineTest: A register mask was used in the tests, made up for register 1 and 2. These registers are the link register and stack pointer on RISC-V and break the tests. A solution using an offset fromcResultRegisteris implemented.VMMachineSimulatorTest: The mapping IR/machine code is not 1-to-1 on RISC-V and breaks the Unicorn count testing. A simple instruction count is added using the size of the generated machine code.Where we are:
All tests passing from a fresh
Pharo12image:The code has been fully generated without errors using:
Next steps:
I am currently trying the to build directly (to avoid cross-compilation for now) on the RISC-V Beagle-V Ahead board and will provide a different pull request adding build instructions and support in the C code for the RISC-V backend.