[arch] Expand addr_width to 48 bits and data_width to 256 bits in src/const.sv

[marcos-mendez]

Upstream uses 32-bit addresses (max 4 GB) and 32-bit data path. For 128 GB+ products and modern cache lines, expand to:

• addr_width = 48 (256 TB physical address space, fits any planned Sail)
• data_width = 256 (32-byte cache line)

Tasks:

• Update src/const.sv parameters
• Audit all upstream code paths that depend on 32-bit assumptions (mem_simulated_delay logic, RISC-V instruction encoding, register file width)
• Update mock memory controller widths
• Add regression test that exercises addresses > 4 GB
• Document the change as ADR-005 (RVA23 + RVV + matrix profile)

References: docs/popsolutions/ADRS.md (ADR-005 placeholder).

[marcos-mendez]

Phase 1 of the migration landed in 57ad63a (canonical) / GitHub mirror:

• Introduced explicit parameter names: xlen (CPU), mem_data_width (256), cache_line_bytes (32), phys_addr_width (48), virt_addr_width (48), cu_count and simd_lanes (per-Sail overridable via -DMAST_CU_COUNT / -DMAST_SIMD_LANES)
• Upstream parameters (data_width, addr_width, instr_width, num_regs, reg_sel_width) preserved verbatim so existing src/*.sv and prot/*.sv modules continue to compile
• Documented taxonomy and per-file migration plan in docs/popsolutions/architecture/PARAMETER_TAXONOMY.md

Phases 2–4 still open (will be tracked as follow-up issues):

• Phase 2: New IP under src/popsolutions/ uses explicit names (entry points: AXI4 controllers, LiteDRAM/LitePCIe adapters, Compute Unit wrapper)
• Phase 3: Per-file migration of upstream src/*.sv from data_width/addr_width to mem_data_width/phys_addr_width where they refer to memory
• Phase 4: Remove legacy aliases (no earlier than 2027)

Not yet closing this issue — waiting on Phase 2 to land at least one new src/popsolutions/ module that uses the new names in earnest.

[marcos-mendez]

Agent 1 picking this up — branch feat/stream-1/wide-addr-test incoming.

Scope: closes the unchecked Phase-1 box "Add regression test that exercises addresses > 4 GB" via a new cocotb test in verif/axi4_mem_model/. Other unchecked boxes (Phase 2–4 per the prior comment) remain open for follow-up issues.

[marcos-mendez]

PR #12 opened with the wide-address regression test (closes Phase-1 box "Add regression test that exercises addresses > 4 GB").

Local run: TESTS=8 PASS=8 FAIL=0 SKIP=0. Awaiting Agent R review (do-not-self-merge per the team operating model).

Authored by Agent 1 (RTL Architect).

[marcos-mendez]

Closing — Phase 1 (the actionable deliverable in this issue, including the regression test for >4 GiB addresses) was completed by PR #12 (merge commit 382364a, merged 2026-05-06T02:24:04Z).

Agent 1 verified on 2026-05-06: 8/8 tests pass on main HEAD 630a7a7, including test_wide_address_single_beat (writes/reads at 0x0000_0100_0000_0080 = 1 TB + offset) and test_wide_address_multi_beat_incr (4-beat INCR at 0xABCD_0000_0040 with bit[47] set).

The wider parameters now live in src/const.sv:61-87 as explicit new names (phys_addr_width=48, mem_data_width=256, xlen=32) per the merged PARAMETER_TAXONOMY.md design that intentionally preserves upstream addr_width=32/data_width=32 as legacy aliases until 2027 (Phase 4 gate).

Phases 2–4 of the migration plan (src/core.sv, src/global_mem_controller.sv, etc. moving from data_width/addr_width to the new explicit names) need separate focused issues. Filing those next.

Authored by Agent R (Reviewer).