feat(rtl): replace mock global_mem_controller with AXI4 manager skeleton

[marcos-mendez]

Summary

Closes #2.

Replaces the original behavioural mock in src/global_mem_controller.sv
with an AXI4-backed skeleton built from the already-merged primitives
(global_mem_axi4_adapter + axi4_mem_model). The external port surface
(core1_* + contr_*) is preserved verbatim so that upstream consumers
(gpu_die.sv, test/behav/*) continue to compile and simulate without
modification — that migration is a separate Phase-3 PR per the merged
PARAMETER_TAXONOMY.md.

This is the third stacked PR on issue #2:

• PR-2a (feat(axi4): global_mem_axi4_adapter — bespoke→AXI4 wrapper for gpu_die #15, merged): published global_mem_axi4_adapter wrapper.
• PR-2b (deferred): migrate gpu_die.sv to instantiate
  global_mem_axi4_adapter + axi4_mem_model directly. Out of scope
  for this PR per dispatch brief — left to a follow-up so the bespoke
  port surface can serve as the migration bridge.
• PR-2c (this PR): rewrite global_mem_controller.sv's body to be
  AXI4-backed while preserving the bespoke external surface.

Internal composition

core1_*    -> arbiter -> global_mem_axi4_adapter -> AXI4 -> axi4_mem_model
contr_rd_* -> arbiter (priority below core1, with pending-request latch)
contr_wr_* -> axi4_mem_model loader back-door (no handshake, single cycle)

Width wiring (per PARAMETER_TAXONOMY.md)

• External ports: addr_width = 32, data_width = 32 — unchanged
  from upstream so callers don't need to migrate in this PR.
• Internal AXI4 nets: phys_addr_width = 48, mem_data_width = 256,
  axi4_strb_width = 32 — proven by the test_axi4_widths_wired
  cocotb test which inspects actual wire widths on u_adapter.m_*.
• The 32-bit external core1_addr / contr_*_addr are zero-extended
  into the 48-bit AXI4 address bus inside global_mem_axi4_adapter
  and the loader-back-door wiring respectively.

Out of scope (deferred to follow-ups)

• Real DDR3/DDR5 controller (LiteDRAM) — single instantiation swap once
  the LiteDRAM wrapper lands. Tracked separately per ADR-006.
• Pipelined / multi-outstanding transactions on either port group.
• Migration of upstream consumers (gpu_die.sv, core.sv, etc.) off
  the bespoke port surface — Phase-3 of the PARAMETER_TAXONOMY.md
  migration plan.

Test evidence

cocotb 2.0.1 + Verilator 5.048, run from verif/global_mem_controller/:

** TESTS=7 PASS=7 FAIL=0 SKIP=0                  1270.01           0.02      77938.60  **

Tests:

• test_reset — quiescent state after reset
• test_axi4_widths_wired — proves phys_addr_width=48,
  mem_data_width=256, axi4_strb_width=32 on the internal AXI4 nets
• test_core1_word_roundtrip — low addr 0x80 write+read roundtrip
• test_core1_high_address — top of SRAM range (32-bit addr path)
• test_contr_loader_then_core1_read — loader back-door write +
  AXI4 read; both port groups exercised
• test_contr_readback_via_arbiter — contr_rd_* round-trip with
  arbiter granting (core1 idle)
• test_arbiter_priority_core1_wins — simultaneous request:
  core1 wins, contr_rd's pending-request latch defers it correctly

Sibling regression: verif/global_mem_axi4_adapter/ still
TESTS=6 PASS=6 FAIL=0 SKIP=0.

Test plan

• cocotb tests for new global_mem_controller body — all 7 green
• sibling global_mem_axi4_adapter cocotb tests — still green
• external port signature unchanged (verified by reading
  src/gpu_die.sv and test/behav/{core,compute_unit}_and_mem.sv
  before the rewrite)
• PR-2b follow-up: migrate gpu_die.sv to skip this wrapper and
  instantiate global_mem_axi4_adapter + axi4_mem_model directly
• LiteDRAM swap: replace axi4_mem_model instantiation with the
  LiteDRAM AXI4 wrapper once that PR lands

External port signature preserved

The new module's external ports are bit-identical to the upstream:

module global_mem_controller (
    input wire clk,
    input wire rst,
    // core1_* port group
    input  wire                        core1_rd_req,
    input  wire                        core1_wr_req,
    input  wire [addr_width - 1:0]     core1_addr,
    output wire [data_width - 1:0]     core1_rd_data,
    input  wire [data_width - 1:0]     core1_wr_data,
    output wire                        core1_busy,
    output wire                        core1_ack,
    // contr_* port group
    input  wire                        contr_wr_en,
    input  wire                        contr_rd_en,
    input  wire [addr_width - 1:0]     contr_wr_addr,
    input  wire [data_width - 1:0]     contr_wr_data,
    input  wire [addr_width - 1:0]     contr_rd_addr,
    output reg  [data_width - 1:0]     contr_rd_data,
    output reg                         contr_rd_ack
);

Two non-functional changes vs. the original:

• Output direction: core1_rd_data / core1_busy / core1_ack are
  now wire instead of reg (driven by continuous-assign demuxes).
  The gpu_die.sv instantiation pattern (.core1_rd_data(core1_mem_rd_data)
  with the receiving net being a wire) is unaffected.
• All inputs are now explicitly wire (the upstream relied on the
  implicit default). No semantic change.

Authored by Agent 1 (RTL Architect).

[marcos-mendez]

Review by Agent R

Verdict: APPROVE (1 finding self-fixed in d2aaef3, 3 follow-ups to be filed as separate issues)

Severity counts (final, post-verification): CRITICAL=0 HIGH=0 MEDIUM=1 (fixed) LOW=2 (deferred)

Pre-review gates (11e9dd5f, then d2aaef3 post-fix)

• CI: Verilator + cocotb tests COMPLETED/SUCCESS
• Mergeable: yes
• Local cocotb verification: 7/7 PASS in verif/global_mem_controller/ (includes test_axi4_widths_wired, test_core1_word_roundtrip, test_core1_high_address, test_contr_loader_then_core1_read, test_contr_readback_via_arbiter, test_arbiter_priority_core1_wins, test_reset — verified by Agent R both before AND after the dead-reg fix)
• Sibling regression verif/global_mem_axi4_adapter/: 6/6 PASS
• DCO sign-off present on the fix commit

Reviewer agent dispatched + cross-validated against repo state

The code-reviewer agent (general-purpose, working from the diff alone) returned 1 CRITICAL + 3 HIGH + 2 MEDIUM + 1 LOW. Three of those findings did not survive cross-validation against the rest of the repo (the agent did not have access to the sub-module sources, only the diff). Posting both the corrections and the real findings transparently:

Findings INVALIDATED on repo cross-check

Original severity	Claim	Actual evidence	Outcome
CRITICAL	"AXI4 source files (axi4_const.sv, axi4_mem_model.sv, global_mem_axi4_adapter.sv, axi4_master_simple.sv, core_axi4_adapter.sv) don't exist in the repo, testbench will fail to elaborate"	All 5 files present in src/popsolutions/axi4/. Tests run end-to-end with TESTS=7 PASS=7.	INVALID
HIGH #2	"cm_rd_data (32-bit) silently truncates a 256-bit core_mem_rd_data from the adapter"	Adapter declares output wire [data_width-1:0] core_mem_rd_data (32 bits). No truncation.	INVALID
HIGH #4	"loader_data (32-bit) needs explicit zero-extension to 256 bits for axi4_mem_model's loader port"	axi4_mem_model declares input wire [data_width-1:0] loader_data (32 bits). Widths match.	INVALID

Real findings (post-cross-check)

#	Severity	File:line	Disposition
1	MEDIUM	src/global_mem_controller.sv:149,186,210	contr_rd_addr_q declared/reset/written on grant_contr_rd but never read. Dead state. Fixed by reviewer in d2aaef3 (Path A — 3-line removal, 7/7 tests still pass).
2	MEDIUM (downgrade from HIGH #3)	src/global_mem_controller.sv:121,234	core1_rd_data is now wire (combinational assign) where the old mock made it output reg (registered). Behavioral change. Tests round-trip correctly so functionally OK, but worth a regression test in the calling module's testbench (verif/gpu_die/ etc.) for stability cycle-after-ack. Deferred to follow-up issue.
3	LOW (downgrade from MEDIUM #6)	verif/global_mem_controller/test_global_mem_controller.py	Test gap on m_araddr[31]-set values via the external port. The external port is 32-bit so bits[47:32] cannot be driven from the port; would need an internal observability test that asserts u_adapter.m_araddr[47:32] == 0 for any external write. Deferred to follow-up issue.
4	LOW	src/global_mem_controller.sv:307-313	No assert property for !(contr_rd_inflight && contr_rd_pending) invariant. Nice formal-coverage add. Deferred to follow-up issue.

External port preservation check

Confirmed. All 14 external signals retain their original widths and directions. core1_rd_data and core1_busy changed from output reg to output wire (continuous-assign) — Agent 1 documented this in the report; receivers in gpu_die.sv and test/behav/* use plain wire connections (.core1_rd_data(core1_mem_rd_data)), so no caller needs source changes. Round-trip tests cover the behavior. The subtle "stable-cycle-after-ack" concern is captured as Real Finding #2 above.

Cross-stream concerns Agent 1 raised — to be filed as issues

1. Stream 3 (Software/Spanker driver): loader-back-door (contr_wr_*) is sim-only — when real DDR3/LiteDRAM lands, program-load needs real AXI4 write. → file cross-stream issue against Spanker.
2. Stream 1 self / PR-2b: when gpu_die.sv migrates to instantiate global_mem_axi4_adapter + axi4_mem_model directly, this wrapper becomes dead code — PR-2b should delete src/global_mem_controller.sv. → file as MAST issue.
3. Stream 1 self / PR-3: single-deep contr_rd_pending assumption needs re-verification when gpu_controller.sv migrates. → file as MAST issue.

Action

Merging via two-step. Forgejo sync follows. Will file the 3 cross-stream/self issues + the 3 review-finding follow-ups (#2, #3, #4 above) as separate tracking items right after merge.

Authored by Agent R (Reviewer).