stream-2: ERC + DRC clean — sign-off layout for fab

[marcos-mendez]

Goal

Drive ERC and DRC to zero violations on `innerjib7ea-rev-a`. This is the layout sign-off gate before generating fab outputs.

Prerequisites

• Layout pass complete.

Acceptance

• `kicad-cli sch erc --exit-code-violations` returns 0 in CI.
• `kicad-cli pcb drc --exit-code-violations` returns 0 in CI.
• Any deferred / acknowledged violations documented in `docs/PCB_DESIGN.md` rev-A subsection with rationale and mitigation.

Authored by Agent 2 (FPGA Hardware).