[LA64_DYNAREC] Add 8bits lock op macros. #3127
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phorcys
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Nov 5, 2025
phorcys
commented
- Add LOCK_8_ALIGNED_4BYTE, LOCK_8_IN_4BYTE macro.
- F0 00 LOCK ADD Eb, Gb
src/dynarec/la64/dynarec_la64_f0.c
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| if (cpuext.lam_bh) { | ||
| AMADD_DB_B(x1, gd, wback); | ||
| } else { | ||
| if (!ALIGNED_ATOMICxw) { |
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This doesn't make sense. Byte atomic can never be unaligned.
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#define ALIGNED_ATOMICxw ((fixedaddress && !(fixedaddress & (((1 << (2 + rex.w)) - 1)))) || BOX64ENV(dynarec_aligned_atomics))
Byte lock opcodes has no "nature alignment"
But LoongArch has only ll.w/sc.w ( amcas_db.b is exceptional)
So I create two macro:
LOCK_8_ALIGNED_4BYTE for 4-byte aligned 8-bits
LOCK_8_IN_4BYTE for 4-byte offset 1/2/3
ALIGNED_ATOMICxw here is to test addr is 4byte aligned or BOX64_DYNAREC_ALIGNED_ATOMICS is turned on.
It's will not emit LOCK_8_IN_4BYTE macro or addr ANDI test.
Else if addr is not 4-byte aligned and BOX64_DYNAREC_ALIGNED_ATOMICS is not turned on ,emit LOCK_8_IN_4BYTE related.
Indeed it looks quite strange, but it should work properly.
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My bad, BOX64_DYNAREC_ALIGNED_ATOMICS should not be tested.
|
By the way, how were these opcodes tested? |
* Add LOCK_8_ALIGNED_4BYTE, LOCK_8_IN_4BYTE macro. * F0 00 LOCK ADD Eb, Gb
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