Update Bender.yml
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Co-authored-by: Jannis Schönleber <joennlae@gmail.com> Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> update `Bender.yml` by using flist and `vendor` deps chore: add one `include` to help pickle bender: add defines `RVFI_TRACE` and remove `instr_tracer` for synth bender: rework bender file using deps bender: add `Bender.lock` file bender: update `Bender.yml` to make it work in `vsim` cheshire: add `cheshire` `axi` changes bender: add `fpga` target with `tc_sram_fpga_wrapper` Revert "cheshire: add `cheshire` `axi` changes" This reverts commit ba95d2e.
This was referenced Mar 7, 2023
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