Added FF-based register file.

Bender.yml

@@ -17,6 +17,7 @@ sources:
       - rtl/hwpe_ctrl_interfaces.sv
       - rtl/hwpe_ctrl_package.sv
       # Level 1
+      - rtl/hwpe_ctrl_regfile_ff.sv
       - rtl/hwpe_ctrl_regfile_latch.sv
       - rtl/hwpe_ctrl_seq_mult.sv
       - rtl/hwpe_ctrl_uloop.sv

rtl/hwpe_ctrl_regfile.sv

@@ -17,6 +17,7 @@
 module hwpe_ctrl_regfile
   import hwpe_ctrl_package::*;
 #(
+  parameter int unsigned REGFILE_SCM    = 1,
   parameter int unsigned N_CONTEXT      = REGFILE_N_CONTEXT,
   parameter int unsigned ID_WIDTH       = 16,
   parameter int unsigned N_IO_REGS      = 2,
@@ -101,9 +102,10 @@ module hwpe_ctrl_regfile
     logic [N_CONTEXT-1:0]                  wren_cxt;
 
     hwpe_ctrl_regfile_latch_test_wrap #(
-      .ADDR_WIDTH(SCM_ADDR_WIDTH),
-      .DATA_WIDTH(32)
-    ) i_regfile_latch (
+      .REGFILE_SCM ( REGFILE_SCM    ),
+      .ADDR_WIDTH  ( SCM_ADDR_WIDTH ),
+      .DATA_WIDTH  ( 32             )
+    ) i_regfile   (
       .clk        ( clk_i                           ),
       .rst_n      ( rst_ni                          ),
       .clear      ( clear_i | r_clear_first_startup ),

rtl/hwpe_ctrl_regfile_ff.sv

@@ -0,0 +1,84 @@
+/* 
+ * hwpe_ctrl_regfile_latch.sv
+ * Francesco Conti <fconti@iis.ee.ethz.ch>
+ *
+ * Copyright (C) 2014-2018 ETH Zurich, University of Bologna
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ * 
+ * Yvan Tortorella <yvan.tortorella@unibo.it>
+ * 
+ */
+
+module hwpe_ctrl_regfile_ff #(
+  parameter  int unsigned AddrWidth = 5,
+  parameter  int unsigned DataWidth = 32,
+  localparam int unsigned NumWords  = 2**AddrWidth,
+  localparam int unsigned NumByte   = DataWidth/8
+)(
+  input  logic                 clk_i  ,
+  input  logic                 rst_ni ,
+  input  logic                 clear_i,
+
+  // Read port
+  input  logic                 ReadEnable_i,
+  input  logic [AddrWidth-1:0] ReadAddr_i  ,
+  output logic [DataWidth-1:0] ReadData_o  ,
+
+  // Write port
+  input  logic                 WriteEnable_i,
+  input  logic [AddrWidth-1:0] WriteAddr_i  ,
+  input  logic [DataWidth-1:0] WriteData_i  ,
+  input  logic [NumByte-1:0]   WriteBE_i    ,
+
+   // Memory content (false paths!)
+  output logic [NumWords-1:0][DataWidth-1:0] MemContent_o
+);
+
+logic [NumWords-1:0][DataWidth-1:0] data_d, data_q;
+
+logic clk_int;
+logic enable, clkg_en;
+
+assign enable = WriteEnable_i & (WriteAddr_i <= NumWords);
+
+assign clkg_en = enable | clear_i;
+
+assign ReadData_o = (ReadEnable_i && (ReadAddr_i <= NumWords)) ? data_q[ReadAddr_i] : '0;
+
+tc_clk_gating i_we_clkg    (
+   .clk_i        ( clk_i   ),
+   .en_i         ( clkg_en ),
+   .test_en_i    ( 1'b0    ),
+   .clk_o        ( clk_int )
+);
+
+for (genvar i = 0; i < NumWords; i++) begin
+  for (genvar j = 0; j < NumByte; j++) begin
+    assign data_d[i][j*8+:8] = (enable && (WriteAddr_i == i)) ? (WriteData_i[j*8+:8] & {8{WriteBE_i[j]}})
+                                                              : data_q[i][j*8+:8];
+  end
+end
+
+always_ff @(posedge clk_int, negedge rst_ni) begin
+  if (~rst_ni)
+    data_q <= '0;
+  else begin
+    if (clear_i)
+      data_q <= '0;
+    else
+      data_q <= data_d;
+  end
+end
+
+for (genvar i = 0; i < NumWords; i++) begin
+  assign MemContent_o[i] = data_q[i];
+end
+
+endmodule : hwpe_ctrl_regfile_ff

rtl/hwpe_ctrl_regfile_latch_test_wrap.sv

@@ -15,6 +15,7 @@
 
 module hwpe_ctrl_regfile_latch_test_wrap
 #(
+   parameter int unsigned REGFILE_SCM = 1,
    parameter ADDR_WIDTH = 5,
    parameter DATA_WIDTH = 32,
    parameter NUM_BYTE   = DATA_WIDTH/8
@@ -82,23 +83,42 @@ module hwpe_ctrl_regfile_latch_test_wrap
    end
 
    assign Q_T = ReadData;
-
-   hwpe_ctrl_regfile_latch #(
-      .ADDR_WIDTH ( ADDR_WIDTH ),
-      .DATA_WIDTH ( DATA_WIDTH ),
-      .NUM_BYTE   ( NUM_BYTE   )
-   ) hwpe_ctrl_regfile_latch_i (
-      .clk         ( clk               ),
-      .rst_n       ( rst_n             ),
-      .clear       ( clear             ),
-      .ReadEnable  ( ReadEnable_muxed  ),
-      .ReadAddr    ( ReadAddr_muxed    ),
-      .ReadData    ( ReadData          ),
-      .WriteEnable ( WriteEnable_muxed ),
-      .WriteAddr   ( WriteAddr_muxed   ),
-      .WriteData   ( WriteData_muxed   ),
-      .WriteBE     ( WriteBE_muxed     ),
-      .MemContent  ( MemContent        )
-   );
+
+   if (REGFILE_SCM == 1) begin : gen_scm_regfile
+     hwpe_ctrl_regfile_latch #(
+        .ADDR_WIDTH ( ADDR_WIDTH ),
+        .DATA_WIDTH ( DATA_WIDTH ),
+        .NUM_BYTE   ( NUM_BYTE   )
+     ) hwpe_ctrl_regfile_latch_i (
+        .clk         ( clk               ),
+        .rst_n       ( rst_n             ),
+        .clear       ( clear             ),
+        .ReadEnable  ( ReadEnable_muxed  ),
+        .ReadAddr    ( ReadAddr_muxed    ),
+        .ReadData    ( ReadData          ),
+        .WriteEnable ( WriteEnable_muxed ),
+        .WriteAddr   ( WriteAddr_muxed   ),
+        .WriteData   ( WriteData_muxed   ),
+        .WriteBE     ( WriteBE_muxed     ),
+        .MemContent  ( MemContent        )
+     );
+   end else begin : gen_ff_regfile
+     hwpe_ctrl_regfile_ff #(
+        .AddrWidth ( ADDR_WIDTH ),
+        .DataWidth ( DATA_WIDTH )
+     ) hwpe_ctrl_regfile_ff_i (
+        .clk_i         ( clk               ),
+        .rst_ni        ( rst_n             ),
+        .clear_i       ( clear             ),
+        .ReadEnable_i  ( ReadEnable_muxed  ),
+        .ReadAddr_i    ( ReadAddr_muxed    ),
+        .ReadData_o    ( ReadData          ),
+        .WriteEnable_i ( WriteEnable_muxed ),
+        .WriteAddr_i   ( WriteAddr_muxed   ),
+        .WriteData_i   ( WriteData_muxed   ),
+        .WriteBE_i     ( WriteBE_muxed     ),
+        .MemContent_o  ( MemContent        )
+     );
+   end
 
 endmodule // hwpe_ctrl_regfile_latch

rtl/hwpe_ctrl_slave.sv

@@ -17,6 +17,7 @@
 module hwpe_ctrl_slave
   import hwpe_ctrl_package::*;
 #(
+  parameter int unsigned REGFILE_SCM    = 1,
   parameter int unsigned N_CORES        = 4,
   parameter int unsigned N_CONTEXT      = 2,
   parameter int unsigned N_EVT          = REGFILE_N_EVT,
@@ -240,6 +241,7 @@ module hwpe_ctrl_slave
   assign regfile_flags.running_context = running_context;
 
   hwpe_ctrl_regfile #(
+    .REGFILE_SCM    ( REGFILE_SCM    ),
     .N_CONTEXT      ( N_CONTEXT      ),
     .N_IO_REGS      ( N_IO_REGS      ),
     .N_GENERIC_REGS ( N_GENERIC_REGS ),