docs+test: spectre/csdb policy + aarch64 CVE audit + arXiv 2604.17391 citation

[avrabe]

Summary

• Adds docs/spectre-policy.md — a per-lowering Spectre / speculative-execution policy for synth's WASM-to-ARM-Cortex-M / RV32 codegen, aligned with the Wasmtime 44.0.0 default (csdb off on aarch64) and using the Crocus (ASPLOS 2024) F/D/A policy taxonomy. 21 rule decisions documented.
• Audits the April 2026 Wasmtime aarch64/x86-64 security advisories for synth analogs:
  • GHSA-jhxm-h53p-jm7w / CVE-2026-34971 (aarch64 Cranelift sandbox escape): a latent analog exists in rules.rs:1887 (the add_with_shift standard rule hard-codes the LSL amount to 2 while pattern-matching any I32Shl;I32Add). Gated today only by the fact that RuleApplicator::apply_rules does not actually rewrite ops to the replacement. A new regression test crates/synth-synthesis/tests/regression_spectre_cve_2026_34971.rs asserts the safety disjunction so the CVE shape can't land silently.
  • GHSA-qqfj-4vcm-26hv / CVE-2026-34944 (x86-64 f64x2.splat over-read): no analog. Documented in §3 of the policy.
• Adds a "Customer narrative" section to the README citing Andreasyan et al., arXiv 2604.17391 — "RISC-V Functional Safety for Autonomous Automotive Systems" — as external academic validation of synth's framing that functional safety is a certification problem, not a processor problem.

Key decisions in spectre-policy.md

• Default to "csdb off" (matches Wasmtime 44.0.0) because synth targets in-order Cortex-M0/M3/M4/M33 and bare-metal RV32IM in a single-tenant threat model — no cross-domain secret to leak. Two rules (Analyze codebase and plan next steps #2 Cortex-M7/M55 software bounds check, Archive or delete obsolete documentation #8 add_with_shift standard rule) are flagged for explicit attention.
• F (fence required): 0 rules today. F (opt-in via future --mitigate-spectre-v1): 1 rule for M7/M55. D (other mitigation suffices): 19 rules. A (accepted residual): 2 rules, both gated (one by a regression test, one by docs).
• The MPU (Cortex-M) and PMP (RV32) hardware boundaries are treated as the architectural Spectre-v1 mitigation for the "BoundsCheckConfig::None" path; AND-masking (BoundsCheckConfig::Masking) is recommended for Cortex-M55 per the Blade (POPL 2021) index-masking result.
• The synth analog of the aarch64 ISLE bug (rule condition broader than replacement) is the unused add_with_shift rule; the regression test makes the latency of the bug explicit and self-checking.

Files changed

• docs/spectre-policy.md (new, ~210 lines)
• crates/synth-synthesis/tests/regression_spectre_cve_2026_34971.rs (new, 2 tests, both passing)
• README.md (new "Customer narrative" section between PulseEngine table and Installation)

Test plan

• cargo test -p synth-synthesis --test regression_spectre_cve_2026_34971 — 2 passed
• cargo test --workspace --exclude synth-verify — all pass (synth-verify excluded due to unrelated bundled-z3 build issue on the dev machine; CI uses the system z3)
• cargo clippy --workspace --all-targets -- -D warnings — clean
• cargo fmt --check — clean
• CI to confirm synth-verify builds via system z3
• (manual) reviewer to sanity-check the 21 rule decisions in §2 against the listed source locations

Scope notes

This PR does not touch:

• optimizer_bridge.rs (PR fix(opt): defensive panic on unmapped vreg instead of silent R0 fallback #101 territory)
• the cargo-fuzz crate (PR feat(fuzz): cargo-fuzz harnesses for ARM instruction selection (#82) #100)
• the i64 semantic tests (PR test: i64 semantic correctness — 25+ tests covering all i64 wasm ops #99)
• feat/riscv-cross-function-calls WIP
• the const-addr load work (PR feat(opt): fold constant address into base+offset for memory ops (#95) #96)

The regression test only reads the public RuleDatabase / RuleApplicator API; it has no overlap with in-flight work.

References:

• Wasmtime v44.0.0 release notes — csdb default change
• Bytecode Alliance 2026-04-09 advisory bulletin
• GHSA-jhxm-h53p-jm7w
• GHSA-qqfj-4vcm-26hv
• Crocus (VanHattum et al., ASPLOS 2024)
• Andreasyan et al., arXiv 2604.17391

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[codecov]

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