feat(vcr-ra)!: SYNTH_SPILL_REALLOC default-on — Belady spilling ships (#242, VCR-RA-001)

[avrabe]

SYNTH_SPILL_REALLOC default-on — Belady spilling ships (#242, VCR-RA-001)

The deliberate byte-changing flip, executed with the refreeze ritual (the v0.14.0 local-promotion pattern). The three-stage spill-realloc lever — #569 slot-value forwarding, #576 Belady spill re-choice, #579 whole-function slot liveness — now runs by default; SYNTH_SPILL_REALLOC=0 is the opt-out (any other value, or unset, runs the pass). SYNTH_SPILL_ON_EXHAUST is untouched (population-changing — stays off pending silicon).

Evidence basis for the flip

• Three landed, flag-off, individually oracle-gated increments (feat(vcr-ra): liveness-based spill re-choice spike, flag-off (#242, VCR-RA-001) #569 → feat(vcr-ra): Belady spill-plan re-choice — flat_flight frame traffic recovered (#242, VCR-RA-001) #576 → feat(vcr-ra): whole-function slot liveness — dead frame stores drop (#242, VCR-RA-001) #579), each with per-segment executable value-trace equality guards, strict-shrink commit gates, and sub-word/unknown-slot conservatism.
• 40+ functions shrink / 0 grow across the 68-fixture × 2-path sweep.
• Full Belady contract met on flat_flight: frame traffic 3ld+3st → 0ld+0st (belady(k=9)=0ld+0st), 412→388 B.

Execution differentials — run on the NEW default bytes BEFORE re-pinning

All unicorn-vs-wasmtime, exit 0:

harness	result
const_cse_differential.py	PASS (all fns match wasmtime, spill12 −88 B with CSE, direct-path gate non-vacuous)
frame_slot_dce_differential.py	PASS — flight_algo 0x07FDF307 on default AND opt-out, 4 arg sets each
flight_seam_differential.py	MATCH — 0x07FDF307 vs wasmtime
spill_rung_581_differential.py	PASS 12/12 (spill_rung_581 + spill_on_exhaust_242 fixtures)
r12_spill_496_differential.py	PASS — control_step_decide 5/5 + flight_algo vs wasmtime
i64_param_518_differential.py	PASS (full AAPCS matrix, loud-skips intact)
br_table_value_509_differential.py	PASS (both paths)

control_step_differential.py has a pre-existing harness break (KeyError control_step_decide in its disasm-text symbol parse — the #489 host-dependence class); it fails identically with SYNTH_SPILL_REALLOC=0, i.e. on the pre-flip bytes, so it is not the flip. Its anchor is covered by r12_spill_496_differential.py vs wasmtime, and control_step's .text is byte-identical under the flip anyway (see table).

Refreeze table (frozen_codegen_bytes.rs, ARM --relocatable gate)

fixture	old sha256 / len	new sha256 / len	Δ
control_step.wasm	1a97711c… / 304	unchanged	0
flight_seam.wasm	dce728b4… / 738	6872d6f3… / 730	−8 B
flight_seam_flat.wasm	0665e623… / 878	d11849db… / 866	−12 B
signed_div_const.wasm	b277453b… / 34	unchanged	0

RV32 anchors: UNCHANGED — the pass is wired only in arm_backend.rs (ARM path); frozen_fixtures_rv32_text_is_bit_identical_oracle_001 passes untouched. The const_cse_reduction_242.rs optimized-path golden (0xa68aa2da…/576) is also byte-identical under the flip — verified, no re-bless needed.

Opt-out pin (CI-gated escape hatch)

• SYNTH_SPILL_REALLOC=0 reproduces the OLD hashes byte-for-byte (verified per fixture, and locked by the new frozen_fixtures_spill_realloc_escape_hatch_restores_old_bytes test — the rollback proof AND a leak tripwire).
• The older SYNTH_NO_STACK_FWD escape hatch now composes with SYNTH_SPILL_REALLOC=0 to reach the pre-STACK_FWD goldens (documented in the test).
• spill_realloc_242.rs flag-on assertions became default assertions; flag-off became the =0 opt-out.

Gate (all foreground, exit 0)

• cargo build -p synth-cli ✓
• Execution differentials (above) BEFORE refreeze ✓
• cargo test -p synth-cli (43+ tests incl. re-pinned frozen gate + both escape hatches) ✓
• cargo test -p synth-synthesis (510+) ✓
• cargo test --workspace --exclude synth-verify ✓
• cargo fmt --check ✓ · cargo clippy --workspace --all-targets -- -D warnings ✓

🤖 Generated with Claude Code

[codecov]

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