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feat: Verus-style contracts with runtime debug_assert! checking#69

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avrabe merged 2 commits intomainfrom
feat/verus-contracts
Mar 28, 2026
Merged

feat: Verus-style contracts with runtime debug_assert! checking#69
avrabe merged 2 commits intomainfrom
feat/verus-contracts

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@avrabe avrabe commented Mar 28, 2026

Summary

Formal specification contracts for critical subsystems, designed for future Verus integration.

contracts.rs (new module)

  • regalloc: R9/R10/R11 exclusion, allocation validation
  • encoding: Thumb-16/32 byte counts, MOVW/MOVT imm16, register ranges
  • memory: access size validation, bounds check with size
  • division: trap guard sequence length

Runtime checks at 13 critical sites

  • Register allocator: alloc_reg, index_to_reg
  • Bounds checking: 4 load/store functions
  • Division: 4 trap guard emissions
  • ARM encoder: MOVW/MOVT, SDIV/UDIV

Path to Verus

These debug_assert! contracts mirror Verus requires/ensures specs.
When rules_verus with verus_strip is ready, wrap in verus!{} blocks
for machine-checked verification.

895 tests (was 885), VG-001/VG-006 in-progress.

Test plan

  • cargo test --workspace — 895 tests, 0 failures
  • Contract violation tests (#[should_panic]) pass
  • cargo clippy — clean

🤖 Generated with Claude Code

Formal specification contracts for synth's critical subsystems,
designed for future Verus integration via rules_verus + verus_strip.

contracts.rs — 4 specification modules:
- regalloc: reserved register exclusion (R9/R10/R11), allocation
  validation, index bounds checking
- encoding: Thumb-16/32 byte count, MOVW/MOVT imm16 range,
  register bit-field range
- memory: access size validation (1/2/4/8), bounds check with size
- division: trap guard sequence length (CMP+BNE+UDF+xDIV >= 4)

Runtime checks inserted at 13 critical sites:
- alloc_reg: pre/post allocation validation
- index_to_reg: allocatable register check
- generate_*_with_bounds_check: access_size precondition (4 sites)
- I32Div*/I32Rem* trap guard: sequence length check (4 sites)
- encode_thumb32_movw/movt: register + immediate range
- SDIV/UDIV encoding: register range + output size

9 unit tests including #[should_panic] for contract violations.
VG-001 and VG-006 status updated to in-progress.

895 tests (was 885), clippy clean, fmt clean.

Implements: VG-001
Implements: VG-006
Trace: skip

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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codecov bot commented Mar 28, 2026

Codecov Report

❌ Patch coverage is 95.55556% with 6 lines in your changes missing coverage. Please review.

Files with missing lines Patch % Lines
crates/synth-synthesis/src/contracts.rs 93.47% 6 Missing ⚠️

📢 Thoughts on this report? Let us know!

The contracts module now contains real Verus spec functions inside
verus! {} blocks. Three compilation modes:

1. Plain cargo: #[cfg(not(verus_keep_ghost))] no-op macro strips specs
2. Verus verification: verus! {} enables machine checking
3. verus_strip (rules_verus @ 24d5ddb5): removes blocks entirely

debug_assert! runtime checks remain alongside the formal specs.
Added #![allow(unexpected_cfgs)] for verus_keep_ghost.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
@avrabe avrabe merged commit 582bdf6 into main Mar 28, 2026
9 checks passed
@avrabe avrabe deleted the feat/verus-contracts branch March 28, 2026 17:37
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