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Cache-Coherence-Simulator

The idea is implementing different protocols to make shared memory among different cores in a chip multiprocessor possible. Protocols implemented include:

  1. MSI
  2. MESI
  3. MOSI
  4. MOESI
  5. MOESIF(also called MOESIsm)

All the header files/hash tables/driver files have not been uploaded because they do not belong to me. I will upload them once i acquire permission to do the same.

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