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Float16 rowwise sparse adagrad with stochastic rounding #370
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277152c
Ref implementation of FP16 fused rowwise sparse adagrad
uyongw 98e16c9
JIT implementation of FP16 fused rowwise sparse adagrad
uyongw 8f0240d
Extend RowWiseSparseAdagradFusedTest with float16 weights update usin…
uyongw 28d46bc
Extend RowwiseAdagradFusedBenchmark with float16 weights update using…
uyongw 2b1e1ca
Fix misc. issues during code review
uyongw ec268b3
Fix missing header x86intrin.h in MSVC build
uyongw 02cfbee
Fix MSVC build on missing symbol of _cvtss_sh/_cvtsh_ss and suppress …
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -8,6 +8,9 @@ cc_library( | |
| includes = [ | ||
| "src", | ||
| ], | ||
| copts = [ | ||
| "-mf16c", | ||
| ], | ||
| deps = [ | ||
| ":fbgemm_headers", | ||
| "@cpuinfo", | ||
|
|
||
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Wouldn't that makes fbgemm code incompatible with SandyBridge CPUs?
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@malfet That would be true. We need perhaps a pure C implementation of _cvtss_sh/_cvtsh_ss in the REF implementation (there is one already but missing the misc. rounding handling). I can create a PR next week for this purpose if needed. @jspark1105
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This PR has been reverted due to an illegal instruction error in PyTorch tests. Let me check if it's related and if so commit with a C implementation.
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Sorry for the introducing this issue. And thanks for the fast turnaround! @jspark1105