Enable ice emmc for kodiak/monaco#702
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sonineerajkumar merged 3 commits intoqualcomm-linux:tech/security/icefrom Mar 13, 2026
Merged
Enable ice emmc for kodiak/monaco#702sonineerajkumar merged 3 commits intoqualcomm-linux:tech/security/icefrom
sonineerajkumar merged 3 commits intoqualcomm-linux:tech/security/icefrom
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March 13, 2026 11:21
Starting with sc7280(kodiak), the ICE will have its own device-tree node. So add the qcom,ice property to reference it. To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE register region in the SDHCI node. Older SoCs without ICE remain valid as no additional requirement is imposed. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…or SDHC Add an ICE node to kodiak SoC description and enable it by adding a phandle to the SDHC node. Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260310113557.348502-3-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
…or SDHC Add an ICE node to monaco SoC description and enable it by adding a phandle to the SDHC node. Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260310113557.348502-4-neeraj.soni@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
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Document Inline Crypto Engine (ICE) handle for SDHC and add its device-tree
node to enable it for kodiak and monaco.
How this patch was tested: