clk: qcom: Add DISPCC and GPUCC support for the Qualcomm Shikra SoC#655
clk: qcom: Add DISPCC and GPUCC support for the Qualcomm Shikra SoC#655imrashai wants to merge 14 commits into
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Drop the older series Shikra GPUCC/DISPCC code chages. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
…from probe Some GCC branch clocks are required to be kept always-on due to the hardware requirements. Drop the modelling of those always-on QCM2290 GCC clocks and use the latest .clk_cbcr convention to keep them enabled from probe. Change-Id: Ie9349d320d3a50ff1386b6b49a849d2f2074e2e3 Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-1-8204f1029311@oss.qualcomm.com
…leep clocks Update the QCM2290 DISPCC binding to document additional clock inputs supported by the hardware, including DSI1 PHY byte/pixel clocks and the sleep clock, alongside the existing clock list. This is an ABI extension, and existing clock inputs ordering is unchanged. Change-Id: I42efe00f96721a833eccc4c43d389c4b1fc6becb Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-2-8204f1029311@oss.qualcomm.com
… controller The Qualcomm Shikra Display clock controller is similar to QCM2290 DISPCC hardware block. Hence, reuse the QCM2290 DISPCC bindings for Qualcomm Shikra SoC. Change-Id: Ia142d9c3e5af3d4e861685c4659fe03e51d04842 Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-3-8204f1029311@oss.qualcomm.com
…troller The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC hardware block, with minor differences. Hence, reuse the QCM2290 GPUCC bindings for Qualcomm Shikra SoC. Change-Id: Ic20afaf9abf0d9b5773ed5e7308c4a660a0c70ae Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-4-8204f1029311@oss.qualcomm.com
…c_probe() model Update the QCM2290 DISPCC driver to use the qcom_cc_probe() model by moving the critical clocks handling and PLL configurations from probe to the driver_data to align with the latest convention. Change-Id: I6fb15fe6c923cf009b160414fe0edf82bd90d5aa Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-5-8204f1029311@oss.qualcomm.com
Update the QCM2290 DISPCC driver to use the DT index based parent clock lookup to align with the latest convention. While at it, fix the parent data of mdss ahb/mdp clocks to use GPLL0 main output as per HW clock plan, and update frequency table accordingly. Also, add the DSI1 PHY PLL input clocks support. Change-Id: I275f3514ccfddd9a14b0143f2ef89321544dd7ed Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-6-8204f1029311@oss.qualcomm.com
… flags Update the QCM2290 DISPCC GDSC wait_val fields to match the hardware default values. Incorrect settings can cause the GDSC FSM to stuck, leading to power on/off failures. And update GDSC flags to retain the registers, and poll for the CFG GDSCR, and switch between HW/SW mode dynamically as per the latest convention. Change-Id: I53fad22ab038f2080506669b4ab06e2288b6156f Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-7-8204f1029311@oss.qualcomm.com
…_probe() model Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving the critical clocks handling and PLL configurations from probe to the driver_data to align with the latest convention. While at it, drop the modelling of gpu_cc_ahb_clk and gpu_cc_cxo_aon_clk clocks and keep them enabled from probe as per the hardware requirements, and drop pm_clk handling as the required GCC clocks are kept always-on from GCC probe. Change-Id: Ia7c0e40c53c09be947c84fedb9a440ae21bd2402 Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-8-8204f1029311@oss.qualcomm.com
…g disable The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Change-Id: Id33903b94da3189458ff0120342283d4f97618c8 Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-9-8204f1029311@oss.qualcomm.com
…flags Update the QCM2290 GPUCC GDSC wait_val fields to match the hardware default values. Incorrect settings can cause the GDSC FSM to stuck, leading to power on/off failures. And update the GPUCC GDSC flags to retain the registers, and poll for the CFG GDSCR as applicable. Change-Id: I3da22ff0372fc41f1910319e4ad9c2b38a30d8a5 Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-10-8204f1029311@oss.qualcomm.com
… Shikra The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC hardware block, with minor differences. Hence add support for Shikra GPUCC by extending the QCM2290 GPUCC driver. Change-Id: Ife9c448f17e631b8c8b9e971c03bb3972412920c Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-11-8204f1029311@oss.qualcomm.com
…DISPCC node Update the DISPCC node on QCM2290 (Agatti) to align with the latest DT bindings changes, which adds support for the DSI1 PHY and sleep clocks. Change-Id: I7d5ce132ef3d6bd9181717aab7722895edc46dce Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-12-8204f1029311@oss.qualcomm.com
Add support for Display clock controller and GPU clock controller nodes on Qualcomm Shikra SoCs. Change-Id: I807a79eb01eb152136e178b7b35ed2d5fa9edc8f Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-13-8204f1029311@oss.qualcomm.com
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PR #655 — validate-patchPR: #655
Final Summary
Additional observations:
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PR #655 — checker-log-analyzerPR: #655
Detailed report: Full report
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Test Matrix
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commit ce0123c upstream. During async unlink, we drop the `i_nlink` counter before we receive the completion (that will eventually update the `i_nlink`) because "we assume that the unlink will succeed". That is not a bad idea, but it races against deletions by other clients (or against the completion of our own unlink) and can lead to an underrun which emits a WARNING like this one: WARNING: CPU: 85 PID: 25093 at fs/inode.c:407 drop_nlink+0x50/0x68 Modules linked in: CPU: 85 UID: 3221252029 PID: 25093 Comm: php-cgi8.1 Not tainted 6.14.11-cm4all1-ampere qualcomm-linux#655 Hardware name: Supermicro ARS-110M-NR/R12SPD-A, BIOS 1.1b 10/17/2023 pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : drop_nlink+0x50/0x68 lr : ceph_unlink+0x6c4/0x720 sp : ffff80012173bc90 x29: ffff80012173bc90 x28: ffff086d0a45aaf8 x27: ffff0871d0eb5680 x26: ffff087f2a64a718 x25: 0000020000000180 x24: 0000000061c88647 x23: 0000000000000002 x22: ffff07ff9236d800 x21: 0000000000001203 x20: ffff07ff9237b000 x19: ffff088b8296afc0 x18: 00000000f3c93365 x17: 0000000000070000 x16: ffff08faffcbdfe8 x15: ffff08faffcbdfec x14: 0000000000000000 x13: 45445f65645f3037 x12: 34385f6369706f74 x11: 0000a2653104bb20 x10: ffffd85f26d73290 x9 : ffffd85f25664f94 x8 : 00000000000000c0 x7 : 0000000000000000 x6 : 0000000000000002 x5 : 0000000000000081 x4 : 0000000000000481 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff08727d3f91e8 Call trace: drop_nlink+0x50/0x68 (P) vfs_unlink+0xb0/0x2e8 do_unlinkat+0x204/0x288 __arm64_sys_unlinkat+0x3c/0x80 invoke_syscall.constprop.0+0x54/0xe8 do_el0_svc+0xa4/0xc8 el0_svc+0x18/0x58 el0t_64_sync_handler+0x104/0x130 el0t_64_sync+0x154/0x158 In ceph_unlink(), a call to ceph_mdsc_submit_request() submits the CEPH_MDS_OP_UNLINK to the MDS, but does not wait for completion. Meanwhile, between this call and the following drop_nlink() call, a worker thread may process a CEPH_CAP_OP_IMPORT, CEPH_CAP_OP_GRANT or just a CEPH_MSG_CLIENT_REPLY (the latter of which could be our own completion). These will lead to a set_nlink() call, updating the `i_nlink` counter to the value received from the MDS. If that new `i_nlink` value happens to be zero, it is illegal to decrement it further. But that is exactly what ceph_unlink() will do then. The WARNING can be reproduced this way: 1. Force async unlink; only the async code path is affected. Having no real clue about Ceph internals, I was unable to find out why the MDS wouldn't give me the "Fxr" capabilities, so I patched get_caps_for_async_unlink() to always succeed. (Note that the WARNING dump above was found on an unpatched kernel, without this kludge - this is not a theoretical bug.) 2. Add a sleep call after ceph_mdsc_submit_request() so the unlink completion gets handled by a worker thread before drop_nlink() is called. This guarantees that the `i_nlink` is already zero before drop_nlink() runs. The solution is to skip the counter decrement when it is already zero, but doing so without a lock is still racy (TOCTOU). Since ceph_fill_inode() and handle_cap_grant() both hold the `ceph_inode_info.i_ceph_lock` spinlock while set_nlink() runs, this seems like the proper lock to protect the `i_nlink` updates. I found prior art in NFS and SMB (using `inode.i_lock`) and AFS (using `afs_vnode.cb_lock`). All three have the zero check as well. Cc: stable@vger.kernel.org Fixes: 2ccb454 ("ceph: perform asynchronous unlink if we have sufficient caps") Signed-off-by: Max Kellermann <max.kellermann@ionos.com> Reviewed-by: Viacheslav Dubeyko <Slava.Dubeyko@ibm.com> Signed-off-by: Ilya Dryomov <idryomov@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This series adds support for the Display clock controller (DISPCC) and GPU Clock Controller (GPUCC) on Qualcomm Shikra SoC, by reusing the respective QCM2290 SoC drivers.
In qcom-6.18.y branch, the Shikra DISPCC/GPUCC v1 series changes are merged already. But as per the upstream comments, we are re-suing the Agatti drivers, and v1 series chagnes are not applicable now. Hence, I have reverted all those v1 specific changes in a commit, and on top of that updated all the latest v4 series changes.
Link to v4: https://lore.kernel.org/all/20260604-shikra-dispcc-gpucc-v4-0-8204f1029311@oss.qualcomm.com
CRs-Fixed: 4560023