Clk gp mnd by taniyadas20 · Pull Request #657 · qualcomm-linux/kernel

taniyadas20 · 2026-06-04T19:24:33Z

The series adds clk: qcom: Add PDM GP_MN fractional clock divider driver and DT support
CRs-Fixed: 4560714

…divider Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN clock divider. The hardware generates a fractional output frequency from a fixed input clock (typically TCXO4) using the relation Fout = Fin * (M / N), with duty cycle controlled by a separate D register. The clock output is routed over a gpio controlled pin. Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

qswat-orbit-external · 2026-06-04T19:24:42Z

Merge Check Failed: No CR Numbers Found

Error: No Change Request numbers were found.

Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests.

taniyadas20 · 2026-06-04T19:41:16Z

https://lore.kernel.org/all/20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com/
CR - https://orbit/CR/4560714

Topic Branch PR--
(DT) qualcomm-linux/kernel-topics#1297
Code qualcomm-linux/kernel-topics#1295

shashim-quic · 2026-06-05T12:12:17Z

_ No description provided. _

CRs-Fixed: missing in PR description

FROMLIST: clk: qcom: Add a driver for PDM GP_MN fractional clock divider

labeled as FROMLIST but misses Link: tag

The PDM (Pulse Density Modulation) hardware block on Qualcomm SoCs contains a GP_MN clock divider that produces a fractional output frequency from a fixed input clock (typically TCXO4): Fout = Fin * (M / N) The hardware encodes the period in the NDIV register as the 1's complement of (N - M), and controls the duty cycle via a separate DUTY register that counts the number of low-phase native clock cycles over the period N. Add a standalone platform driver for this block that uses rational_best_approximation() to find the closest M/N pair within the 9-bit M and 13-bit N hardware limits, programs the MDIV, NDIV, and DUTY registers via regmap, and implements the full clk_ops surface including determine_rate, set_rate, recalc_rate, get_duty_cycle, and set_duty_cycle. The PDM AHB bus clock is gated around every register access. Link: https://lore.kernel.org/all/20260602-pdm_clk_gp_mnd_v1-v1-2-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

…and SC7280 Add the gp_mn pin mux function to the TLMM pin controllers for the QCS8300, SA8775P and SC7280 SoCs. This function exposes the GP M/N divider clock output on a dedicated GPIO pin, allowing the clock signal to be routed externally. - QCS8300: gpio32 - SA8775P: gpio35 - SC7280: gpio60 Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-3-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Add pinctrl states for the GP M/N divider clock output pin across multiple Qualcomm SoCs: wire it to the GP M/N clock controller node via pinctrl-0. - sc7280 (sc7280): Add gp_mn_active state on gpio35 (gp_mn function). - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

…75P and QCS8300 Add the GP M/N divider clock controller node at 0x088d3000 to the SA8775P (sc7280, lemans) and QCS8300 (monaco) SoC device trees. The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM XO4 and AHB clocks from GCC, and exposes a single clock output (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock is pre-assigned to 4.8 MHz (XO/4). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

qswat-orbit-external · 2026-06-05T17:18:00Z

Merge Check Failed: No CR Numbers Found

Error: No Change Request numbers were found.

Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests.

qswat-orbit-external · 2026-06-05T17:19:50Z

Merge Check Failed: No CR Numbers Found

Error: No Change Request numbers were found.

Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests.

qlijarvis · 2026-06-05T18:21:35Z

PR #657 — validate-patch

PR: #657

Verdict	Issues	Detailed Report
❌	3	Full report

Final Summary

Lore link present: Yes — all 5 commits have lore.kernel.org Link tags with message-ID format
Lore link matches PR commits: Cannot verify — lore links return empty (patches dated 2026-06-02 not yet accessible on lore.kernel.org)
Upstream patch status: Not upstream — FROMLIST prefix indicates patches intended for upstream but not yet posted or still in review
PR present in qcom-next: Not checked — FROMLIST patches are pre-upstream submissions

Verdict: ❌ — click to expand

🔍 Patch Validation

PR: #657
Title: Add PDM GP_MN fractional clock divider driver and device tree support
Upstream commit: Not yet posted (FROMLIST patches dated 2026-06-02)
Verdict: ❌ FAIL

Commit Message

Check Status Note

Subject format ✅ All subjects follow kernel style with subsystem prefix

Body clarity ✅ Clear technical descriptions with hardware details

Link tag present ✅ All 5 commits have lore.kernel.org Link tags

Authorship preserved ✅ Consistent author: Taniya Das taniya.das@oss.qualcomm.com

Sign-off present ✅ All commits properly signed off

FROMLIST prefix ✅ Correctly marked as FROMLIST (not yet upstream)

Diff

File Status Notes

Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml ✅ New binding doc, proper YAML format, SPDX header present

drivers/clk/qcom/clk-gp-mnd.c ✅ New driver, proper SPDX header, clean implementation

drivers/clk/qcom/Kconfig ✅ Config entry added correctly

drivers/clk/qcom/Makefile ✅ Build rule added correctly

drivers/pinctrl/qcom/pinctrl-qcs8300.c ✅ gp_mn function added to gpio32

drivers/pinctrl/qcom/pinctrl-sa8775p.c ✅ gp_mn function added to gpio35

drivers/pinctrl/qcom/pinctrl-sc7280.c ✅ gp_mn function added to gpio60

arch/arm64/boot/dts/qcom/lemans.dtsi (patch 4) ✅ Pinctrl state uses gpio35 (matches driver)

arch/arm64/boot/dts/qcom/monaco.dtsi (patch 4) ✅ Pinctrl state uses gpio32 (matches driver)

arch/arm64/boot/dts/qcom/sc7280.dtsi (patch 4) ❌ CRITICAL: Uses gpio35 but driver defines gpio60

arch/arm64/boot/dts/qcom/lemans.dtsi (patch 5) ✅ Clock controller node correct

arch/arm64/boot/dts/qcom/monaco.dtsi (patch 5) ✅ Clock controller node correct

arch/arm64/boot/dts/qcom/sc7280.dtsi (patch 5) ✅ Clock controller node correct

Issues

CRITICAL BUG - GPIO Pin Mismatch for SC7280:
Patch 3 (pinctrl driver) correctly adds gp_mn function to gpio60 for SC7280:
static const char *const gp_mn_groups[] = {
    "gpio60",
};
[60] = PINGROUP(60, qup17, edp_hot, gp_mn, phase_flag, _, _, _, _, _),
Patch 4 (DTS pinctrl state) incorrectly uses gpio35 for SC7280:
Commit message says: "sc7280 (sc7280): Add gp_mn_active state on gpio35"
Actual diff shows:
+			gp_mn_active: gp_mn_active-state {
+				pins = "gpio35";
+				function = "gp_mn";
Impact: The device tree will fail to apply the pinctrl state because gpio35 does not have the gp_mn function defined in the pinctrl driver. This will cause runtime errors when the clock controller driver attempts to configure the pin.

Fix Required: Change pins = "gpio35"; to pins = "gpio60"; in arch/arm64/boot/dts/qcom/sc7280.dtsi (patch 4), and update the commit message accordingly.
Other observations:

SA8775P (lemans) correctly uses gpio35 in both driver and DTS

QCS8300 (monaco) correctly uses gpio32 in both driver and DTS

Link tag in patch 2 uses /all/ while others use /r/ (both valid, but inconsistent)

Verdict

REJECT - Critical bug in patch 4 causes SC7280 device tree to reference non-existent pin function. The pinctrl state must use gpio60 to match the driver definition.

Final Summary

Lore link present: Yes — all 5 commits have lore.kernel.org Link tags with message-ID format

Lore link matches PR commits: Cannot verify — lore links return empty (patches dated 2026-06-02 not yet accessible on lore.kernel.org)

Upstream patch status: Not upstream — FROMLIST prefix indicates patches intended for upstream but not yet posted or still in review

PR present in qcom-next: Not checked — FROMLIST patches are pre-upstream submissions

qlijarvis · 2026-06-05T18:21:36Z

PR #657 — checker-log-analyzer

PR: #657
Checker run: https://github.com/qualcomm-linux/kernel-config/actions/runs/27029495066

Checker	Result	Summary
Checker	Result	Summary
checkpatch	❌	2 alignment style issues in clk-gp-mnd.c
dt-binding-check	✅	Passed
dtb-check	❌	gp_mn function not in pinctrl binding schemas
sparse-check	✅	Passed
check-uapi-headers	✅	Passed
check-patch-compliance	❌	Commit 4/5 differs from lore link
tag-check	N/A	FROMLIST commits
qcom-next-check	⏭️	FROMLIST commits only

Detailed report: Full report

Checker analysis — click to expand

🤖 CI Checker Analysis (checker-log-analyzer)

PR: #657 - FROMLIST: Add PDM GP_MN clock divider support
Source: https://github.com/qualcomm-linux/kernel-config/actions/runs/27029495066

Checker Result Summary

checkpatch ❌ 2 alignment style issues in clk-gp-mnd.c

dt-binding-check ✅ Passed

dtb-check ❌ gp_mn function not in pinctrl binding schemas

sparse-check ✅ Passed

check-uapi-headers ✅ Passed

check-patch-compliance ❌ Commit 4/5 differs from lore link

tag-check N/A FROMLIST commits

qcom-next-check ⏭️ FROMLIST commits only

❌ checkpatch

Root cause: Two function parameter alignments don't match open parenthesis in drivers/clk/qcom/clk-gp-mnd.c

Failure details:
CHECK: Alignment should match open parenthesis
#155: FILE: drivers/clk/qcom/clk-gp-mnd.c:79:
+static int gp_mnd_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)

CHECK: Alignment should match open parenthesis
#207: FILE: drivers/clk/qcom/clk-gp-mnd.c:131:
+static unsigned long gp_mnd_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
Fix: Align continuation lines with the opening parenthesis:
static int gp_mnd_clk_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)

static unsigned long gp_mnd_clk_recalc_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
Reproduce locally:
./scripts/checkpatch.pl --strict --summary-file --ignore FILE_PATH_CHANGES \
  --git 997c1ece634c..cd6b879cf133
❌ dtb-check

Root cause: The gp_mn pinmux function was added to pinctrl driver code but not to the corresponding DT binding YAML schemas for qcom,sc7280-pinctrl, qcom,sa8775p-tlmm, and qcom,qcs8300-tlmm.

Failure details:
/arch/arm64/boot/dts/qcom/sc7280-idp.dtb: pinctrl@f100000 (qcom,sc7280-pinctrl): 
  gp_mn_active-state: 'oneOf' conditional failed, one must be fixed:
    'gp_mn' is not one of ['atest_char', 'atest_char0', ..., 'vsense_trigger']

/arch/arm64/boot/dts/qcom/lemans-evk.dtb: pinctrl@f000000 (qcom,sa8775p-tlmm): 
  gp_mn_active-state: 'oneOf' conditional failed, one must be fixed:
    'gp_mn' is not one of ['atest_char', 'atest_usb2', ..., 'vsense_trigger']

/arch/arm64/boot/dts/qcom/monaco-ac-evk.dtb: pinctrl@f100000 (qcom,qcs8300-tlmm): 
  gp_mn_active-state: 'oneOf' conditional failed, one must be fixed:
    'gp_mn' is not one of ['aoss_cti', 'atest_char', ..., 'vsense_trigger']
Fix: Add gp_mn to the function enum list in these three DT binding files:

Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml

Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml

Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml

In each file, add gp_mn to the function property enum list (alphabetically between gpio and the next entry, or after gcc_gp5 depending on the file's ordering).

Reproduce locally:
make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
make dtbs_check W=1
❌ check-patch-compliance

Root cause: Commit 4/5 ("FROMLIST: arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output") has local changes that differ from the upstream lore patch.

Failure details:
Checking commit: FROMLIST: arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output
Change is different from the one mentioned in Link
Fix: Either:

Ensure the patch exactly matches the lore version at https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com, or

If intentional local modifications were made, document them in the commit message below the Link: tag with a note like "[ Qualcomm-linux: modified to include XYZ ]"

Reproduce locally:
# Fetch the lore patch and compare
b4 am 20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com
git show 019769a5c8bb > local.patch
diff -u v1_*.mbx local.patch
Verdict

3 blockers must be fixed before merge:

Fix checkpatch alignment issues in drivers/clk/qcom/clk-gp-mnd.c

Add gp_mn function to pinctrl DT binding schemas for SC7280, SA8775P, and QCS8300

Reconcile commit 4/5 with its lore upstream or document local changes

qcomlnxci · 2026-06-05T19:37:13Z

Test jobs on cd6b879

qcomlnxci · 2026-06-05T19:37:13Z

Test Matrix

Test Case	lemans-evk	monaco-evk	qcs615-ride	qcs6490-rb3gen2	qcs8300-ride	qcs9100-ride-r3	x1e80100-crd
BT_FW_KMD_Service	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
BT_ON_OFF	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
BT_SCAN	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
CPUFreq_Validation	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
CPU_affinity	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
DSP_AudioPD	✅ Pass	◻️	⚠️ skip	✅ Pass	✅ Pass	⚠️ skip	◻️
Ethernet	⚠️ skip	◻️	⚠️ skip	⚠️ skip	⚠️ skip	⚠️ skip	◻️
Freq_Scaling	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
GIC	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
IPA	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
Interrupts	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
OpenCV	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
PCIe	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
Probe_Failure_Check	❌ Fail	◻️	❌ Fail	❌ Fail	❌ Fail	❌ Fail	◻️
RMNET	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
UFS_Validation	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
USBHost	❌ Fail	◻️	❌ Fail	❌ Fail	❌ Fail	❌ Fail	◻️
WiFi_Firmware_Driver	❌ Fail	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
WiFi_OnOff	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
adsp_remoteproc	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	❌ Fail	◻️
cdsp_remoteproc	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	❌ Fail	◻️
gpdsp_remoteproc	✅ Pass	◻️	⚠️ skip	⚠️ skip	✅ Pass	❌ Fail	◻️
hotplug	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
irq	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
kaslr	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
pinctrl	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
qcom_hwrng	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
remoteproc	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	❌ Fail	◻️
rngtest	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
shmbridge	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
smmu	❌ Fail	◻️	❌ Fail	✅ Pass	✅ Pass	❌ Fail	◻️
watchdog	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️
wpss_remoteproc	✅ Pass	◻️	✅ Pass	✅ Pass	✅ Pass	✅ Pass	◻️

taniyadas20 requested review from a team, knaveen-qc, ndechesne and quicAspratap June 4, 2026 19:24

taniyadas20 added 4 commits June 5, 2026 22:47

taniyadas20 force-pushed the clk-gp-mnd branch from cd44d98 to cd6b879 Compare June 5, 2026 17:17

shashim-quic approved these changes Jun 5, 2026

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qlijarvis commented Jun 5, 2026

PR #657 — validate-patch

Final Summary

🔍 Patch Validation

Commit Message

Diff

Issues

Verdict

Final Summary

Uh oh!

qlijarvis commented Jun 5, 2026

PR #657 — checker-log-analyzer

🤖 CI Checker Analysis (checker-log-analyzer)

❌ checkpatch

❌ dtb-check

❌ check-patch-compliance

Verdict

Uh oh!

qcomlnxci commented Jun 5, 2026

Test jobs on cd6b879

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