Proposal
I would like to promote five Thumb-mode bare-metal Arm targets to Tier 2, to join their Arm-mode counterparts which are already Tier 2:
| Thumb-mode target (Tier 3 → Tier 2) |
Arm-mode counterpart (already Tier 2) |
thumbv7a-none-eabi |
armv7a-none-eabi |
thumbv7a-none-eabihf |
armv7a-none-eabihf |
thumbv7r-none-eabi |
armv7r-none-eabi |
thumbv7r-none-eabihf |
armv7r-none-eabihf |
thumbv8r-none-eabihf |
armv8r-none-eabihf |
Note: There is no thumbv8r-none-eabi target because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary.
These Thumb-mode targets generate T32 (Thumb-2) code by default, while their Arm-mode counterparts generate A32 code by default. The two instruction sets share the same LLVM backend, the same ABI (EABI/EABIhf), and the same data layout. The only differences in the target specifications are the llvm_target string and the description. Promoting them to Tier 2 will provide pre-compiled core and alloc artifacts via rustup, making it easier for embedded developers to use Thumb-mode without -Zbuild-std.
Many embedded projects prefer Thumb-mode for its smaller code size, and Cortex-R and Cortex-A processors support both modes. Having both modes at Tier 2 ensures parity and removes the current inconsistency where Arm-mode is Tier 2 but Thumb-mode is Tier 3.
The PR is rust-lang/rust#155763
Process
The main points of the Major Change Process are as follows:
You can read more about Major Change Proposals on forge.
Proposal
I would like to promote five Thumb-mode bare-metal Arm targets to Tier 2, to join their Arm-mode counterparts which are already Tier 2:
thumbv7a-none-eabiarmv7a-none-eabithumbv7a-none-eabihfarmv7a-none-eabihfthumbv7r-none-eabiarmv7r-none-eabithumbv7r-none-eabihfarmv7r-none-eabihfthumbv8r-none-eabihfarmv8r-none-eabihfNote: There is no
thumbv8r-none-eabitarget because the Cortex-R52 processor always includes an FPU, making a soft-float ABI variant unnecessary.These Thumb-mode targets generate T32 (Thumb-2) code by default, while their Arm-mode counterparts generate A32 code by default. The two instruction sets share the same LLVM backend, the same ABI (EABI/EABIhf), and the same data layout. The only differences in the target specifications are the
llvm_targetstring and the description. Promoting them to Tier 2 will provide pre-compiledcoreandallocartifacts via rustup, making it easier for embedded developers to use Thumb-mode without-Zbuild-std.Many embedded projects prefer Thumb-mode for its smaller code size, and Cortex-R and Cortex-A processors support both modes. Having both modes at Tier 2 ensures parity and removes the current inconsistency where Arm-mode is Tier 2 but Thumb-mode is Tier 3.
The PR is rust-lang/rust#155763
Process
The main points of the Major Change Process are as follows:
@rustbot secondor kickoff a team FCP with@rfcbot fcp $RESOLUTION.You can read more about Major Change Proposals on forge.