Auto merge of #149531 - Zalathar:rollup-15y580s, r=<try>

Rollup of 8 pull requests

try-job: x86_64-msvc-1
try-job: i686-msvc-1
try-job: x86_64-mingw-1
try-job: test-various
try-job: armhf-gnu
try-job: aarch64-apple
try-job: dist-various-1

Author: rust-bors[bot]

compiler/rustc_target/src/spec/base/thumb.rs renamed to compiler/rustc_target/src/spec/base/arm_none.rs

@@ -1,31 +1,4 @@
-// These `thumbv*` targets cover the ARM Cortex-M family of processors which are widely used in
-// microcontrollers. Namely, all these processors:
-//
-// - Cortex-M0
-// - Cortex-M0+
-// - Cortex-M1
-// - Cortex-M3
-// - Cortex-M4(F)
-// - Cortex-M7(F)
-// - Cortex-M23
-// - Cortex-M33
-//
-// We have opted for these instead of one target per processor (e.g., `cortex-m0`, `cortex-m3`,
-// etc) because the differences between some processors like the cortex-m0 and cortex-m1 are almost
-// nonexistent from the POV of codegen so it doesn't make sense to have separate targets for them.
-// And if differences exist between two processors under the same target, rustc flags can be used to
-// optimize for one processor or the other.
-//
-// Also, we have not chosen a single target (`arm-none-eabi`) like GCC does because this makes
-// difficult to integrate Rust code and C code. Targeting the Cortex-M4 requires different gcc flags
-// than the ones you would use for the Cortex-M0 and with a single target it'd be impossible to
-// differentiate one processor from the other.
-//
-// About arm vs thumb in the name. The Cortex-M devices only support the Thumb instruction set,
-// which is more compact (higher code density), and not the ARM instruction set. That's why LLVM
-// triples use thumb instead of arm. We follow suit because having thumb in the name let us
-// differentiate these targets from our other `arm(v7)-*-*-gnueabi(hf)` targets in the context of
-// build scripts / gcc flags.
+// These are the baseline settings for 32-bit bare-metal Arm targets using the EABI or EABIHF ABI.
 
 use crate::spec::{Cc, FramePointer, LinkerFlavor, Lld, PanicStrategy, RelocModel, TargetOptions};
 

compiler/rustc_target/src/spec/base/mod.rs

@@ -1,6 +1,7 @@
 pub(crate) mod aix;
 pub(crate) mod android;
 pub mod apple;
+pub(crate) mod arm_none;
 pub(crate) mod avr;
 pub(crate) mod bpf;
 pub(crate) mod cygwin;
@@ -31,7 +32,6 @@ pub(crate) mod redox;
 pub(crate) mod solaris;
 pub(crate) mod solid;
 pub(crate) mod teeos;
-pub(crate) mod thumb;
 pub(crate) mod uefi_msvc;
 pub(crate) mod unikraft_linux_musl;
 pub(crate) mod vxworks;

compiler/rustc_target/src/spec/targets/armv4t_none_eabi.rs

@@ -9,10 +9,7 @@
 //! The default link script is very likely wrong, so you should use
 //! `-Clink-arg=-Tmy_script.ld` to override that with a correct linker script.
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions, cvs,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -25,35 +22,16 @@ pub(crate) fn target() -> Target {
         },
         pointer_width: 32,
         arch: Arch::Arm,
-        /* Data layout args are '-' separated:
-         * little endian
-         * stack is 64-bit aligned (EABI)
-         * pointers are 32-bit
-         * i64 must be 64-bit aligned (EABI)
-         * mangle names with ELF style
-         * native integers are 32-bit
-         * All other elements are default
-         */
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
             asm_args: cvs!["-mthumb-interwork", "-march=armv4t", "-mlittle-endian",],
-            // Force-enable 32-bit atomics, which allows the use of atomic load/store only.
-            // The resulting atomics are ABI incompatible with atomics backed by libatomic.
-            features: "+soft-float,+strict-align,+atomics-32".into(),
-            main_needs_argc_argv: false,
+            features: "+soft-float,+strict-align".into(),
             atomic_cas: false,
+            max_atomic_width: Some(0),
             has_thumb_interworking: true,
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
-            // From thumb_base, rust-lang/rust#44993.
-            emit_debug_gdb_scripts: false,
-            // From thumb_base, GCC gives enums a minimum of 8 bits on no-os targets.
-            c_enum_min_bits: Some(8),
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/armv5te_none_eabi.rs

@@ -1,8 +1,6 @@
 //! Targets the ARMv5TE, with code as `a32` code by default.
 
-use crate::spec::{
-    Abi, Arch, FloatAbi, FramePointer, Target, TargetMetadata, TargetOptions, base, cvs,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -15,36 +13,16 @@ pub(crate) fn target() -> Target {
         },
         pointer_width: 32,
         arch: Arch::Arm,
-        /* Data layout args are '-' separated:
-         * little endian
-         * stack is 64-bit aligned (EABI)
-         * pointers are 32-bit
-         * i64 must be 64-bit aligned (EABI)
-         * mangle names with ELF style
-         * native integers are 32-bit
-         * All other elements are default
-         */
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
-
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-            // extra args passed to the external assembler (assuming `arm-none-eabi-as`):
-            // * activate t32/a32 interworking
-            // * use arch ARMv5TE
-            // * use little-endian
             asm_args: cvs!["-mthumb-interwork", "-march=armv5te", "-mlittle-endian",],
-            // minimum extra features, these cannot be disabled via -C
-            // Also force-enable 32-bit atomics, which allows the use of atomic load/store only.
-            // The resulting atomics are ABI incompatible with atomics backed by libatomic.
-            features: "+soft-float,+strict-align,+atomics-32".into(),
-            frame_pointer: FramePointer::MayOmit,
-            main_needs_argc_argv: false,
-            // don't have atomic compare-and-swap
+            features: "+soft-float,+strict-align".into(),
             atomic_cas: false,
+            max_atomic_width: Some(0),
             has_thumb_interworking: true,
-
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv4t_none_eabi.rs

@@ -9,10 +9,7 @@
 //! The default link script is very likely wrong, so you should use
 //! `-Clink-arg=-Tmy_script.ld` to override that with a correct linker script.
 
-use crate::spec::{
-    Abi, Arch, FloatAbi, FramePointer, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions, base, cvs,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -25,44 +22,16 @@ pub(crate) fn target() -> Target {
         },
         pointer_width: 32,
         arch: Arch::Arm,
-        /* Data layout args are '-' separated:
-         * little endian
-         * stack is 64-bit aligned (EABI)
-         * pointers are 32-bit
-         * i64 must be 64-bit aligned (EABI)
-         * mangle names with ELF style
-         * native integers are 32-bit
-         * All other elements are default
-         */
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-
-            // extra args passed to the external assembler (assuming `arm-none-eabi-as`):
-            // * activate t32/a32 interworking
-            // * use arch ARMv4T
-            // * use little-endian
             asm_args: cvs!["-mthumb-interwork", "-march=armv4t", "-mlittle-endian",],
-
-            // minimum extra features, these cannot be disabled via -C
-            // Also force-enable 32-bit atomics, which allows the use of atomic load/store only.
-            // The resulting atomics are ABI incompatible with atomics backed by libatomic.
-            features: "+soft-float,+strict-align,+atomics-32".into(),
-
-            panic_strategy: PanicStrategy::Abort,
-            relocation_model: RelocModel::Static,
-            // suggested from thumb_base, rust-lang/rust#44993.
-            emit_debug_gdb_scripts: false,
-            frame_pointer: FramePointer::MayOmit,
-
-            main_needs_argc_argv: false,
-
-            // don't have atomic compare-and-swap
+            features: "+soft-float,+strict-align".into(),
             atomic_cas: false,
+            max_atomic_width: Some(0),
             has_thumb_interworking: true,
-
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv5te_none_eabi.rs

@@ -1,8 +1,6 @@
 //! Targets the ARMv5TE, with code as `t32` code by default.
 
-use crate::spec::{
-    Abi, Arch, FloatAbi, FramePointer, Target, TargetMetadata, TargetOptions, base, cvs,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -15,36 +13,16 @@ pub(crate) fn target() -> Target {
         },
         pointer_width: 32,
         arch: Arch::Arm,
-        /* Data layout args are '-' separated:
-         * little endian
-         * stack is 64-bit aligned (EABI)
-         * pointers are 32-bit
-         * i64 must be 64-bit aligned (EABI)
-         * mangle names with ELF style
-         * native integers are 32-bit
-         * All other elements are default
-         */
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
-
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-            // extra args passed to the external assembler (assuming `arm-none-eabi-as`):
-            // * activate t32/a32 interworking
-            // * use arch ARMv5TE
-            // * use little-endian
             asm_args: cvs!["-mthumb-interwork", "-march=armv5te", "-mlittle-endian",],
-            // minimum extra features, these cannot be disabled via -C
-            // Also force-enable 32-bit atomics, which allows the use of atomic load/store only.
-            // The resulting atomics are ABI incompatible with atomics backed by libatomic.
-            features: "+soft-float,+strict-align,+atomics-32".into(),
-            frame_pointer: FramePointer::MayOmit,
-            main_needs_argc_argv: false,
-            // don't have atomic compare-and-swap
+            features: "+soft-float,+strict-align".into(),
             atomic_cas: false,
+            max_atomic_width: Some(0),
             has_thumb_interworking: true,
-
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv6m_none_eabi.rs

@@ -26,7 +26,7 @@ pub(crate) fn target() -> Target {
             // There are no atomic CAS instructions available in the instruction set of the ARMv6-M
             // architecture
             atomic_cas: false,
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv6m_nuttx_eabi.rs

@@ -25,7 +25,7 @@ pub(crate) fn target() -> Target {
             // The ARMv6-M doesn't support hardware atomic operations, use atomic builtins instead.
             features: "+strict-align".into(),
             max_atomic_width: Some(32),
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv7a_nuttx_eabi.rs

@@ -27,7 +27,7 @@ pub(crate) fn target() -> Target {
             // Cortex-A7/A8/A9 with software floating point
             features: "+soft-float,-neon".into(),
             max_atomic_width: Some(64),
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv7a_nuttx_eabihf.rs

@@ -31,7 +31,7 @@ pub(crate) fn target() -> Target {
             // and NEON SIMD instructions
             features: "+vfp3,+neon".into(),
             max_atomic_width: Some(64),
-            ..base::thumb::opts()
+            ..base::arm_none::opts()
         },
     }
 }