explicitly track SPE ABI for PowerPC

Author: RalfJung

compiler/rustc_target/src/spec/mod.rs

@@ -1006,6 +1006,8 @@ crate::target_spec_enum! {
     pub enum RustcAbi {
         /// On x86-32 only: make use of SSE and SSE2 for ABI purposes.
         X86Sse2 = "x86-sse2",
+        /// On PowerPC only: build for SPE.
+        PowerPcSpe = "powerpc-spe",
         /// On x86-32/64, aarch64, and S390x: do not use any FPU or SIMD registers for the ABI.
         Softfloat = "softfloat", "x86-softfloat",
     }
@@ -3445,13 +3447,15 @@ impl Target {
                     "`llvm_abiname` is unused on PowerPC"
                 );
                 check!(self.llvm_floatabi.is_none(), "`llvm_floatabi` is unused on PowerPC");
-                check!(self.rustc_abi.is_none(), "`rustc_abi` is unused on PowerPC");
-                // FIXME: Check that `target_abi` matches the actually configured ABI (with or
-                // without SPE).
                 check_matches!(
+                    (&self.rustc_abi, &self.cfg_abi),
+                    (Some(RustcAbi::PowerPcSpe), CfgAbi::Spe)
+                        | (None, CfgAbi::Unspecified | CfgAbi::Other(_)),
+                    "invalid PowerPC Rust-specific ABI and `cfg(target_abi)` combination:\n\
+                    Rust-specific ABI: {:?}\n\
+                    cfg(target_abi): {}",
+                    self.rustc_abi,
                     self.cfg_abi,
-                    CfgAbi::Spe | CfgAbi::Unspecified | CfgAbi::Other(_),
-                    "invalid `target_abi` for PowerPC"
                 );
             }
             Arch::PowerPC64 => {

compiler/rustc_target/src/spec/targets/powerpc_unknown_linux_gnuspe.rs

@@ -1,8 +1,8 @@
 use rustc_abi::Endian;
 
 use crate::spec::{
-    Arch, Cc, CfgAbi, LinkerFlavor, Lld, StackProbeType, Target, TargetMetadata, TargetOptions,
-    base,
+    Arch, Cc, CfgAbi, LinkerFlavor, Lld, RustcAbi, StackProbeType, Target, TargetMetadata,
+    TargetOptions, base,
 };
 
 pub(crate) fn target() -> Target {
@@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
         arch: Arch::PowerPC,
         options: TargetOptions {
             cfg_abi: CfgAbi::Spe,
+            rustc_abi: Some(RustcAbi::PowerPcSpe),
             endian: Endian::Big,
             features: "+secure-plt,+msync,+spe".into(),
             mcount: "_mcount".into(),

compiler/rustc_target/src/spec/targets/powerpc_unknown_linux_muslspe.rs

@@ -1,8 +1,8 @@
 use rustc_abi::Endian;
 
 use crate::spec::{
-    Arch, Cc, CfgAbi, LinkerFlavor, Lld, StackProbeType, Target, TargetMetadata, TargetOptions,
-    base,
+    Arch, Cc, CfgAbi, LinkerFlavor, Lld, RustcAbi, StackProbeType, Target, TargetMetadata,
+    TargetOptions, base,
 };
 
 pub(crate) fn target() -> Target {
@@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
         arch: Arch::PowerPC,
         options: TargetOptions {
             cfg_abi: CfgAbi::Spe,
+            rustc_abi: Some(RustcAbi::PowerPcSpe),
             endian: Endian::Big,
             features: "+msync,+spe".into(),
             mcount: "_mcount".into(),

compiler/rustc_target/src/spec/targets/powerpc_wrs_vxworks_spe.rs

@@ -1,8 +1,8 @@
 use rustc_abi::Endian;
 
 use crate::spec::{
-    Arch, Cc, CfgAbi, LinkerFlavor, Lld, StackProbeType, Target, TargetMetadata, TargetOptions,
-    base,
+    Arch, Cc, CfgAbi, LinkerFlavor, Lld, RustcAbi, StackProbeType, Target, TargetMetadata,
+    TargetOptions, base,
 };
 
 pub(crate) fn target() -> Target {
@@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
         arch: Arch::PowerPC,
         options: TargetOptions {
             cfg_abi: CfgAbi::Spe,
+            rustc_abi: Some(RustcAbi::PowerPcSpe),
             endian: Endian::Big,
             // feature msync would disable instruction 'fsync' which is not supported by fsl_p1p2
             features: "+secure-plt,+msync,+spe".into(),

compiler/rustc_target/src/target_features.rs

@@ -1178,6 +1178,7 @@ impl Target {
                         // LLVM handles the rest.
                         FeatureConstraints { required: &["soft-float"], incompatible: &[] }
                     }
+                    _ => unreachable!(),
                 }
             }
             Arch::X86_64 => {
@@ -1198,7 +1199,7 @@ impl Target {
                         // LLVM handles the rest.
                         FeatureConstraints { required: &["soft-float"], incompatible: &[] }
                     }
-                    Some(r) => panic!("invalid Rust ABI for x86_64: {r:?}"),
+                    _ => unreachable!(),
                 }
             }
             Arch::Arm => {
@@ -1235,7 +1236,7 @@ impl Target {
                         // `FeatureConstraints` uses Rust feature names, hence only "neon" shows up.
                         FeatureConstraints { required: &["neon"], incompatible: &[] }
                     }
-                    Some(r) => panic!("invalid Rust ABI for aarch64: {r:?}"),
+                    _ => unreachable!(),
                 }
             }
             Arch::RiscV32 | Arch::RiscV64 => {
@@ -1312,17 +1313,32 @@ impl Target {
                         // llvm will switch to soft-float ABI just based on this feature.
                         FeatureConstraints { required: &["soft-float"], incompatible: &["vector"] }
                     }
-                    Some(r) => {
-                        panic!("invalid Rust ABI for s390x: {r:?}");
+                    _ => unreachable!(),
+                }
+            }
+            Arch::PowerPC => {
+                // The main ABI-relevant target features are "hard-float" and "spe". We use our own
+                // ABI indicator here.
+                match self.rustc_abi {
+                    None => {
+                        // Default hardfloat ABI.
+                        FeatureConstraints { required: &["hard-float"], incompatible: &["spe"] }
+                    }
+                    Some(RustcAbi::PowerPcSpe) => {
+                        // We reject "efpu2" since that seems to *disable* the f64 registers in
+                        // LLVM, which seems likely to affect the ABI.
+                        FeatureConstraints {
+                            required: &["hard-float", "spe"],
+                            incompatible: &["efpu2"],
+                        }
                     }
+                    _ => unreachable!(),
                 }
             }
-            Arch::PowerPC | Arch::PowerPC64 => {
-                // The main ABI-relevant target features are "hard-float" and "spe". There is also
-                // "efpu2" but that seems only relevant when "spe" is enabled. If we ever add a
-                // soft-float variant, it looks like we have to mark "altivec" as incompatible --
-                // unlike other targets, it looks like enabling "altivec" will have LLVM use
-                // different registers for float types even if "hard-float" is off.
+            Arch::PowerPC64 => {
+                // There's no SPE for PowerPC64, and we currently don't support any soft-float
+                // targets. (If we ever add one, we need to match on `RustcAbi::Softfloat` similar
+                // to other targets above.)
                 FeatureConstraints { required: &["hard-float"], incompatible: &["spe"] }
             }
             Arch::Avr => {