Add riscv64 uefi target

[gjbauer]

Add riscv64gc-unknown-uefi target

This PR includes the bare minimum changes currently required to include a riscv64gc-unknown-uefi target into the Rust compiler source tree. A few minor changes totally a handful of lines were required outside of the target's target.rs to get the build process to complete successfully, but these should not impose any challenges to existing targets.

One edit was made to the -unknown-uefi.md supported targets Markdown file to mention the existence of a tier 3 target. Since this target will originate as a tier 3 target, it will not be included in rustup for installation. I am willing to make more changes to the Markdown document in order to document how to build, install, and use this new target. Thank you for your consideration of this pull request!!

[rustbot]

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

These commits modify compiler targets.
(See the Target Tier Policy.)

[rustbot]

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[rustbot]

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  • 106cbdd

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  $ git push --force-with-lease
  

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     };
     let binary_format = sess.target.binary_format.to_object();
-    
+
     if sess.target.arch == Arch::RiscV64 && binary_format == BinaryFormat::Coff {
         // Return None to use the fallback mechanism in create_wrapper_file
         // Use this fallback specifically for RISC-V 64 UEFI
Diff in /checkout/compiler/rustc_codegen_llvm/src/back/write.rs:1191:
         // We need custom section flags, so emit module-level inline assembly.
         // The "n" flags is currently not supported on RISC-V
         let mut section_flags = "";
-        if cgcx.target_arch != "riscv64"
-        {
-         if cgcx.is_pe_coff { section_flags = "n" } else { section_flags = "e" };
+        if cgcx.target_arch != "riscv64" {
+            if cgcx.is_pe_coff {
+                section_flags = "n"
+            } else {
+                section_flags = "e"
+            };
         }
         let asm = create_section_with_flags_asm(".llvmbc", section_flags, bitcode);
         llvm::append_module_inline_asm(llmod, &asm);
Diff in /checkout/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs:1:
-use crate::spec::{
- Arch, Target, TargetMetadata, base
-};
+use crate::spec::{Arch, Target, TargetMetadata, base};
 
 pub(crate) fn target() -> Target {
     // Get the base UEFI configuration
Diff in /checkout/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs:7:
     let mut base = base::uefi_msvc::opts();
-    
+
     // Override with RISC-V specific settings
     base.cpu = "generic-rv64".into();
     base.features = "+m,+a,+f,+d,+c".into();
Diff in /checkout/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs:25:
         pointer_width: 64,
         data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
         arch: Arch::RiscV64,
-        
+
         options: base,
     }
 }

[bjorn3]

Why is this necessary?

[bjorn3]

Is there a full coff specification for riscv nowadays or are relocations still not supported on riscv? If the latter then how would you even use this target in the first place?