Add support for AArch64 SHA extensions.

coresimd/aarch64/mod.rs

@@ -13,3 +13,6 @@ pub use self::v8::*;
 
 mod neon;
 pub use self::neon::*;
+
+mod crypto;
+pub use self::crypto::*;

coresimd/aarch64/neon.rs

@@ -2,11 +2,11 @@
 
 // FIXME: replace neon with asimd
 
+use coresimd::arm::*;
+use coresimd::simd::*;
+use coresimd::simd_llvm::simd_add;
 #[cfg(test)]
 use stdsimd_test::assert_instr;
-use coresimd::simd_llvm::simd_add;
-use coresimd::simd::*;
-use coresimd::arm::*;
 
 types! {
     /// ARM-specific 64-bit wide vector of one packed `f64`.
@@ -382,10 +382,10 @@ pub unsafe fn vminvq_f64(a: float64x2_t) -> f64 {
 
 #[cfg(test)]
 mod tests {
-    use stdsimd_test::simd_test;
-    use simd::*;
     use coresimd::aarch64::*;
+    use simd::*;
     use std::mem;
+    use stdsimd_test::simd_test;
 
     #[simd_test = "neon"]
     unsafe fn test_vadd_f64() {

coresimd/arm/neon.rs

@@ -1,9 +1,9 @@
 //! ARMv7 NEON intrinsics
 
+use coresimd::simd::*;
+use coresimd::simd_llvm::*;
 #[cfg(test)]
 use stdsimd_test::assert_instr;
-use coresimd::simd_llvm::*;
-use coresimd::simd::*;
 
 types! {
     /// ARM-specific 64-bit wide vector of eight packed `i8`.
@@ -682,10 +682,10 @@ pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
 
 #[cfg(test)]
 mod tests {
-    use stdsimd_test::simd_test;
-    use simd::*;
     use coresimd::arm::*;
+    use simd::*;
     use std::mem;
+    use stdsimd_test::simd_test;
 
     #[simd_test = "neon"]
     unsafe fn test_vadd_s8() {

coresimd/mips/msa.rs

@@ -5,9 +5,9 @@
 //!
 //! [msa_ref]: http://cdn2.imgtec.com/documentation/MD00866-2B-MSA32-AFP-01.12.pdf
 
+use coresimd::simd::*;
 #[cfg(test)]
 use stdsimd_test::assert_instr;
-use coresimd::simd::*;
 
 #[allow(improper_ctypes)]
 extern "C" {
@@ -28,9 +28,9 @@ pub unsafe fn __msa_add_a_b(a: i8x16, b: i8x16) -> i8x16 {
 
 #[cfg(test)]
 mod tests {
+    use coresimd::mips64::msa;
     use simd::*;
     use stdsimd_test::simd_test;
-    use coresimd::mips64::msa;
 
     #[simd_test = "msa"]
     unsafe fn __msa_add_a_b() {

coresimd/mod.rs

@@ -77,8 +77,8 @@ pub mod arch {
     #[cfg(any(target_arch = "aarch64", dox))]
     #[doc(cfg(target_arch = "aarch64"))]
     pub mod aarch64 {
-        pub use coresimd::arm::*;
         pub use coresimd::aarch64::*;
+        pub use coresimd::arm::*;
     }
 
     /// Platform-specific intrinsics for the `wasm32` platform.
@@ -115,10 +115,10 @@ mod x86;
 #[cfg(any(target_arch = "x86_64", dox))]
 mod x86_64;
 
-#[cfg(any(target_arch = "arm", target_arch = "aarch64", dox))]
-mod arm;
 #[cfg(any(target_arch = "aarch64", dox))]
 mod aarch64;
+#[cfg(any(target_arch = "arm", target_arch = "aarch64", dox))]
+mod arm;
 #[cfg(target_arch = "wasm32")]
 mod wasm32;
 

coresimd/ppsv/api/cmp.rs

@@ -99,11 +99,16 @@ macro_rules! impl_bool_cmp {
 
 #[cfg(test)]
 macro_rules! test_cmp {
-    ($id:ident, $elem_ty:ident, $bool_ty:ident,
-     $true:expr, $false:expr) => {
+    (
+        $id: ident,
+        $elem_ty: ident,
+        $bool_ty: ident,
+        $true: expr,
+        $false: expr
+    ) => {
         #[test]
         fn cmp() {
-            use ::coresimd::simd::*;
+            use coresimd::simd::*;
 
             let a = $id::splat($false);
             let b = $id::splat($true);
@@ -139,5 +144,5 @@ macro_rules! test_cmp {
             let r = a.lt(b);
             assert!(r == e);
         }
-    }
+    };
 }

coresimd/ppsv/api/load_store.rs

@@ -130,8 +130,8 @@ macro_rules! impl_load_store {
             pub unsafe fn load_unaligned_unchecked(
                 slice: &[$elem_ty]
             ) -> Self {
-                use slice::SliceExt;
                 use mem::size_of;
+                use slice::SliceExt;
                 let target_ptr =
                     slice.get_unchecked(0) as *const $elem_ty as *const u8;
                 let mut x = Self::splat(0 as $elem_ty);

coresimd/ppsv/api/minmax_reductions.rs

@@ -22,8 +22,8 @@ macro_rules! impl_minmax_reductions {
             pub fn max(self) -> $elem_ty {
                 // FIXME: broken on AArch64
                 // https://bugs.llvm.org/show_bug.cgi?id=36796
-                use num::Float;
                 use cmp::Ord;
+                use num::Float;
                 let mut x = self.extract(0);
                 for i in 1..$id::lanes() {
                     x = x.max(self.extract(i));
@@ -49,8 +49,8 @@ macro_rules! impl_minmax_reductions {
             pub fn min(self) -> $elem_ty {
                 // FIXME: broken on AArch64
                 // https://bugs.llvm.org/show_bug.cgi?id=36796
-                use num::Float;
                 use cmp::Ord;
+                use num::Float;
                 let mut x = self.extract(0);
                 for i in 1..$id::lanes() {
                     x = x.min(self.extract(i));

coresimd/ppsv/mod.rs

@@ -33,19 +33,19 @@
 #[macro_use]
 mod api;
 
-mod v16;
-mod v32;
-mod v64;
 mod v128;
+mod v16;
 mod v256;
+mod v32;
 mod v512;
+mod v64;
 
-pub use self::v16::*;
-pub use self::v32::*;
-pub use self::v64::*;
 pub use self::v128::*;
+pub use self::v16::*;
 pub use self::v256::*;
+pub use self::v32::*;
 pub use self::v512::*;
+pub use self::v64::*;
 
 /// Safe lossless bitwise conversion from `T` to `Self`.
 pub trait FromBits<T>: ::marker::Sized {

coresimd/ppsv/v128.rs

@@ -121,13 +121,17 @@ use coresimd::arch::aarch64::{// FIXME: float16x8_t,
                               uint8x16_t};
 
 macro_rules! from_bits_arm {
-    ($id:ident, $elem_ty:ident, $test_mod_arm:ident, $test_mod_a64:ident) => {
-        #[cfg(any(all(target_arch = "arm",
-                      target_feature = "neon",
-                      target_feature = "v7"), target_arch = "aarch64"))]
+    (
+        $id: ident,
+        $elem_ty: ident,
+        $test_mod_arm: ident,
+        $test_mod_a64: ident
+    ) => {
+        #[cfg(any(all(target_arch = "arm", target_feature = "neon",
+                      target_feature = "v7"),
+                  target_arch = "aarch64"))]
         impl_from_bits_!(
-            $id:
-            int8x16_t,
+            $id: int8x16_t,
             uint8x16_t,
             int16x8_t,
             uint16x8_t,
@@ -141,10 +145,8 @@ macro_rules! from_bits_arm {
             poly16x8_t
         );
         #[cfg(target_arch = "aarch64")]
-        impl_from_bits_!(
-            $id: float64x2_t
-        );
-    }
+        impl_from_bits_!($id: float64x2_t);
+    };
 }
 
 impl_from_bits!(

coresimd/ppsv/v64.rs

@@ -101,13 +101,17 @@ use coresimd::arch::aarch64::{// FIXME: float16x4_t,
                               uint8x8_t};
 
 macro_rules! from_bits_arm {
-    ($id:ident, $elem_ty:ident, $test_mod_arm:ident, $test_mod_a64:ident) => {
-        #[cfg(any(all(target_arch = "arm",
-                      target_feature = "neon",
-                      target_feature = "v7"), target_arch = "aarch64"))]
+    (
+        $id: ident,
+        $elem_ty: ident,
+        $test_mod_arm: ident,
+        $test_mod_a64: ident
+    ) => {
+        #[cfg(any(all(target_arch = "arm", target_feature = "neon",
+                      target_feature = "v7"),
+                  target_arch = "aarch64"))]
         impl_from_bits_!(
-            $id:
-            int64x1_t,
+            $id: int64x1_t,
             uint64x1_t,
             uint32x2_t,
             int32x2_t,
@@ -121,10 +125,8 @@ macro_rules! from_bits_arm {
             poly8x8_t
         );
         #[cfg(target_arch = "aarch64")]
-        impl_from_bits_!(
-            $id: float64x1_t
-        );
-    }
+        impl_from_bits_!($id: float64x1_t);
+    };
 }
 
 impl_from_bits!(

coresimd/x86/avx.rs

@@ -13,8 +13,8 @@
 //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
-use coresimd::simd_llvm::*;
 use coresimd::simd::*;
+use coresimd::simd_llvm::*;
 use coresimd::x86::*;
 use intrinsics;
 use mem;
@@ -142,9 +142,18 @@ pub unsafe fn _mm256_shuffle_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
 pub unsafe fn _mm256_shuffle_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
     let imm8 = (imm8 & 0xFF) as u8;
     macro_rules! shuffle4 {
-        ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g: expr, $h: expr) => {
+        (
+            $a: expr,
+            $b: expr,
+            $c: expr,
+            $d: expr,
+            $e: expr,
+            $f: expr,
+            $g: expr,
+            $h: expr
+        ) => {
             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
-        }
+        };
     }
     macro_rules! shuffle3 {
         ($a: expr, $b: expr, $c: expr, $e: expr, $f: expr, $g: expr) => {
@@ -471,9 +480,18 @@ pub unsafe fn _mm256_blend_pd(a: __m256d, b: __m256d, imm8: i32) -> __m256d {
 pub unsafe fn _mm256_blend_ps(a: __m256, b: __m256, imm8: i32) -> __m256 {
     let imm8 = (imm8 & 0xFF) as u8;
     macro_rules! blend4 {
-        ($a:expr, $b:expr, $c:expr, $d:expr, $e:expr, $f:expr, $g:expr, $h:expr) => {
+        (
+            $a: expr,
+            $b: expr,
+            $c: expr,
+            $d: expr,
+            $e: expr,
+            $f: expr,
+            $g: expr,
+            $h: expr
+        ) => {
             simd_shuffle8(a, b, [$a, $b, $c, $d, $e, $f, $g, $h]);
-        }
+        };
     }
     macro_rules! blend3 {
         ($a: expr, $b: expr, $c: expr, $d: expr, $e: expr, $f: expr) => {