Skip to content
View rusunited2's full-sized avatar

Block or report rusunited2

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
rusunited2/README.md

Hi there 👋

🔭 I’m currently working on my learning and improving:

1. SystemVerilog Fundamentals and AI Accelerator project

2. UVM Fundamentals and Projects

3. Python skills further by creating a personal project every day (37/100 Projects so far!)

🌱 I’m currently learning new RTL design and Verification concepts to enhance my portfolio

📫 How to reach me: Connect with me https://www.linkedin.com/in/russelsofia/

Pinned Loading

  1. systemverilog_ai_accelerator systemverilog_ai_accelerator Public

    Custom AI accelerator design implemented in SystemVerilog, demonstrating advanced RTL design, verification, and performance analysis techniques.

  2. systemverilog_fundamentals systemverilog_fundamentals Public

    Practical SystemVerilog code repository showcasing foundational learning and early experimentation.

    SystemVerilog

  3. EECS151_FPGA_PROJECT EECS151_FPGA_PROJECT Public

    Verilog 2

  4. fpga_labs_fa22 fpga_labs_fa22 Public

    Forked from EECS150/fpga_labs_fa22

    Verilog

  5. CS61A_Projects CS61A_Projects Public

    JavaScript

  6. rusunited2 rusunited2 Public

    My personal repository.