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feat: Add FPGA Transformer backend crates#105

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ruvnet merged 4 commits intomainfrom
claude/fpga-transformer-backend-2Jk8x
Jan 4, 2026
Merged

feat: Add FPGA Transformer backend crates#105
ruvnet merged 4 commits intomainfrom
claude/fpga-transformer-backend-2Jk8x

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@ruvnet ruvnet commented Jan 4, 2026

Implements ruvector-fpga-transformer and ruvector-fpga-transformer-wasm:

  • TransformerBackend trait with 4 implementations:

    • NativeSimBackend (pure Rust simulator)
    • FpgaDaemonBackend (Unix socket/TCP daemon client)
    • FpgaPcieBackend (DMA ring buffer for PCIe FPGA)
    • WasmSimBackend (WASM-compatible simulator)
  • Core types for deterministic, fixed-shape inference:

    • FixedShape (seq_len, d_model, heads, d_head, vocab)
    • QuantSpec (INT4/INT8 quantization with explicit metadata)
    • GateHint, GateDecision for coherence gating
  • Artifact format with Ed25519 signed bundles:

    • ModelArtifact with manifest, weights, bitstream, test vectors
    • Verification and packing utilities
  • Quantization subsystem:

    • LUT-based softmax, exp, sigmoid, GELU
    • Fixed-point Q8.8 and Q16.16 formats
    • Calibration utilities
  • Gating subsystem for coherence control:

    • CoherenceGate trait with preflight/checkpoint/write
    • DefaultCoherenceGate and MincutCoherenceGate
  • WitnessLog for audit trails and ReasoningBank integration

  • WASM bindings and C FFI layer

  • 58 tests passing across all modules

claude added 4 commits January 4, 2026 05:38
Implements ruvector-fpga-transformer and ruvector-fpga-transformer-wasm:

- TransformerBackend trait with 4 implementations:
  - NativeSimBackend (pure Rust simulator)
  - FpgaDaemonBackend (Unix socket/TCP daemon client)
  - FpgaPcieBackend (DMA ring buffer for PCIe FPGA)
  - WasmSimBackend (WASM-compatible simulator)

- Core types for deterministic, fixed-shape inference:
  - FixedShape (seq_len, d_model, heads, d_head, vocab)
  - QuantSpec (INT4/INT8 quantization with explicit metadata)
  - GateHint, GateDecision for coherence gating

- Artifact format with Ed25519 signed bundles:
  - ModelArtifact with manifest, weights, bitstream, test vectors
  - Verification and packing utilities

- Quantization subsystem:
  - LUT-based softmax, exp, sigmoid, GELU
  - Fixed-point Q8.8 and Q16.16 formats
  - Calibration utilities

- Gating subsystem for coherence control:
  - CoherenceGate trait with preflight/checkpoint/write
  - DefaultCoherenceGate and MincutCoherenceGate

- WitnessLog for audit trails and ReasoningBank integration

- WASM bindings and C FFI layer

- 58 tests passing across all modules
Security fixes addressing audit findings:

1. Artifact unpacking (pack.rs):
   - Add maximum size limits to prevent unbounded allocations
   - MAX_MANIFEST_SIZE: 1 MB
   - MAX_WEIGHTS_SIZE: 1 GB
   - MAX_BLOB_SIZE: 100 MB (bitstream/calibration)
   - MAX_TEST_VECTORS: 10,000
   - MAX_TOKENS_PER_VECTOR: 65,536
   - MAX_EXPECTED_PER_VECTOR: 1,000,000

2. C FFI (c_abi.rs):
   - Replace .unwrap() with checked Layout::array allocation
   - Return null pointers on allocation failure instead of panic
   - Prevents crash from malicious C callers with huge sizes

3. Quantization (quant/mod.rs):
   - Add q15_dot_saturating() for overflow-safe large vector ops
   - Uses saturating_add/saturating_mul to prevent wraparound

All 58 tests passing.
…y hardening

Backend improvements:
- FpgaPcie: Add DMA model upload with bump allocator for FPGA DDR memory
- FpgaDaemon: Implement model load/unload protocol with checksum validation
- WasmSim: Full RefCell-based implementation for single-threaded WASM
- NativeSim: Update to use common utilities

Common utilities extracted to mod.rs:
- compute_topk: Heap-based selection for efficient top-K computation
- read_lock/write_lock: RwLock helpers with poison error handling
- validate_tokens: Token bounds checking against vocabulary size
- build_witness: Witness log construction helper
- commands: Protocol command constants for daemon communication

Security improvements:
- RwLock poison handling prevents panics on poisoned locks
- Token validation prevents out-of-bounds vocabulary access
- Memory allocation tracking for FPGA DDR management
- Checksum validation for daemon protocol integrity

All 61 tests passing.
- Clear intro explaining what the library does and why
- Quick start code example for immediate usage
- Feature comparison tables (backends, shapes, quantization)
- Coherence gating explanation with code examples
- Witness logging documentation
- Backend selection guide with code samples
- Feature flags reference table
- Performance tips section
- ASCII architecture diagram
- Testing and examples instructions
@ruvnet ruvnet merged commit ae4d5db into main Jan 4, 2026
6 checks passed
ruvnet added a commit that referenced this pull request Feb 20, 2026
@ruvnet ruvnet deleted the claude/fpga-transformer-backend-2Jk8x branch April 21, 2026 20:30
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2 participants