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feat: xHCI endpoint matching, EP0 GET_REPORT, MSI hardening#238

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ryanbreen merged 1 commit intomainfrom
feat/parallels-arm64
Feb 22, 2026
Merged

feat: xHCI endpoint matching, EP0 GET_REPORT, MSI hardening#238
ryanbreen merged 1 commit intomainfrom
feat/parallels-arm64

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Summary

  • xHCI driver overhaul to match Linux's exact initialization sequence on Parallels ARM64 virtual xHC (NEC uPD720200 emulation)
  • Batch ConfigureEndpoint with all endpoints in a single command, followed by per-endpoint Drop+Add toggle reset — matching Linux's xhci_check_bandwidth + xhci_endpoint_reset flow
  • EP0 GET_REPORT polling provides working keyboard input at 4Hz via control transfers while interrupt endpoint CC=12 issue is investigated
  • GIC MSI hardening: DSB+ISB barriers on SPI enable/disable to prevent interrupt storms from Parallels virtual xHC
  • Comprehensive heartbeat diagnostics (30+ atomic counters) for xHCI state monitoring without log-based debugging

Changes

  • kernel/src/drivers/usb/xhci.rs: Major rewrite — batch endpoint config, Drop+Add reset, EP0 polling, deferred TRB queueing, endpoint state diagnostics
  • kernel/src/arch_impl/aarch64/gic.rs: DSB+ISB barriers on SPI enable/disable
  • kernel/src/arch_impl/aarch64/timer_interrupt.rs: Extended heartbeat with xHCI transfer/error/doorbell/endpoint diagnostics
  • kernel/src/drivers/usb/descriptors.rs: BOS descriptor type, SET_INTERFACE, SET_ISOCH_DELAY, SET_REPORT requests
  • kernel/src/drivers/mod.rs: Raw serial debug breadcrumbs for xHCI init path
  • .gitignore: Exclude esp/ build artifact and debug capture files

Status

Interrupt endpoint transfers still return CC=12 (Endpoint Not Enabled) on the Parallels virtual xHC despite endpoint contexts matching Linux byte-for-byte. EP0 control transfers work correctly. Investigation ongoing.

Test plan

  • Kernel boots on Parallels ARM64 with timer dots visible
  • EP0 GET_REPORT keyboard polling returns valid HID reports
  • Heartbeat diagnostics display correctly in serial output
  • No MSI interrupt storms after GIC barrier fixes

🤖 Generated with Claude Code

…SI hardening

Major xHCI driver overhaul to match Linux's exact initialization sequence
on Parallels ARM64 virtual xHC (NEC uPD720200). Key changes:

- Batch ConfigureEndpoint with all endpoints in single command (matches Linux)
- Drop+Add toggle reset per endpoint after initial ConfigureEndpoint
- Full 32-byte Slot Context copy matching Linux xhci_slot_copy
- Mult=0 for non-isochronous endpoints per xHCI spec §6.2.3
- EP0 GET_REPORT polling for keyboard input (working at 4Hz)
- Deferred TRB queueing after SPI enable to avoid race conditions
- GIC DSB+ISB barriers on SPI enable/disable to prevent MSI storms
- Comprehensive heartbeat diagnostics for xHCI state monitoring
- USB descriptor additions: BOS, SET_INTERFACE, SET_ISOCH_DELAY, SET_REPORT
- MAX_SLOTS increased to 32 to match Linux CONFIG value
- .gitignore: exclude esp/ build artifact and debug capture files

Interrupt endpoint transfers still return CC=12 (Endpoint Not Enabled),
investigation ongoing. EP0 control transfers work correctly.

Co-Authored-By: Ryan Breen <rbreen@gmail.com>
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
@ryanbreen ryanbreen merged commit bb43b4c into main Feb 22, 2026
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