Notes on OrangeCrab 85F ECP5 fpga dev board experiments.
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11 Try PicoRV32 (work in progress, includes .bit files)
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10 Try VexRiscv (nope)
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09 Try Verilog Examples (includes .dfu files)
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08 More OpenOCD JTAG (also, openFPGALoader + Tigard examples)
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05 Try Riscv Examples (includes .dfu files)
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04 Try Prebuilt Firmware (links to prebuilt .dfu files)
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Gateware: Github orangecrab-fpga/production-test-sw: Software, firmware, and gateware for OrangeCrab test fixture (probably a good starting point to understand how DFU boot mode works). The prebuilt directory has prebuilt bootloader and firmware images. The current 85F prebuilt bootloader is from 2021. Based on 1BitSquared #orangecrab Discord (Feb 2024), it has a file size limit carried over from the 25F bootloader, so fully utilizing the gateware capacity of an r0.2.1 85F probably requires a patched bootloader to be flashed over jtag.
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Examples: Github orangecrab-fpga/orangecrab-examples: Example projects and code for OrangeCrab (probably good starting point for learning how to build riscv SoCs with Litex or Amaranth)
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Old CircuitPython Example: Github gregdavill/circuitpython (orangecrab branch): 4 year old CircuitPython port for OrangeCrab (likely broken or incomplete? but it has interesting Litex stuff.)
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Bootloader: Github gregdavill/foboot (OrangeCrab branch): OrangeCrab bootloader based on the Fomu bootloader. See notes above about prebuilt bootloader and firmware files in orangecrab-fpga/production-test-sw.
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ecpprog: Github gregdavill/ecpprog: ECP5 JTAG programmer that works with FTDI-based JTAG probes (including the FT2232H).
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openOCD config (OrangeCrab): Github orangecrab-hardware/contrib/openocd/orangecrab-85f.cfg: openOCD config for OrangeCrab 85F with FTDI JTAG probe. This config is set up for USB device
0403:6010, which is the default product ID for the FTDI FT2232H/D (source: FTDI's Utilities page, search for "6010"). -
openOCD config (Tigard): Gitub tigard-tools/tigard/README.md: The main README includes an openOCD config for Tigard JTAG (compare to the OrangeCrab openOCD config above).
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orangecrab-fpga.github.io/orangecrab-hardware: HTML docs with hardware specs, pinouts, and Getting Started guide
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GroupGets OrangeCrab product page (scroll down for various links in the product description)
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orangecrab-fpga/orangecrab-hardware (Github): for r0.2.1 schematic pdf, see hardware/orangecrab_r0.2.1/Production/OrangeCrab_r0.2.1_sch.pdf
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mwelling/orangecrab-test (Github): Design files for Orangecrab test fixture. Maybe useful for understanding what factory test firmware does? Schematic is at orangecrab-test.pdf
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DigiKey OrangeCrab r0.2 data sheet
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ulx3s.github.io: Project homepage for ULX3S. The Projects and Examples and Toolchains and Utilities sections probably have useful information on building ECP5 gateware and firmware that could be adapted for use on OrangeCrab.
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ulx3s/ulx3s-toolchain (Github): Scripts for installing ULX3S toolchain, including RISC-V compiler.
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YosysHQ (Github): Open Source EDA CAD suite with projects including Yosys, nextpnr, and Project Trellis
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YosysHQ/yosys (Github): Open RTL synthesis tools to translate Verilog and SystemVerilog into RTL. (Litex depends on this)
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YosysHQ/nextpnr (Github): Portable FPGA place and route tool to translate RTL into an FPGA-specific bitstream.
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YosysHQ/prjtrellis (Github): Documentation for Lattice ECP5 bitstream format and internal architecture. This may be useful for learning about which ECP5 features are available in nextpnr and how to make use of them.
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danderson/ulxs LPF file format specification (Github): Notes on using Lattice Preference File (LPF) file format to tell nextpnr how to configure the ECP5 FPGA. This was cited on 1BitSquared #orangecrab Discord as a good source of info on configuring pin drive strength and slew rate.
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Embecosm Tool Chain Downloads: Prebuilt RISC-V toolchains with GNU binutils, gcc or clang compiler, gdb, and Newlib C standard library.
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embecosm/embecosm-toolchain-releases (Github): Build scripts and related dependencies for Embecosm toolchains. This could be useful as a reference for building C standard libraries for specific RISC-V instruction set extension combinations.
- Lattice Semiconductor ECP5 product page: for ECP5 family data sheet and related guides, scroll down to the Documentation heading
These links are for the OrangeCrab 85F, which uses the 85F variant of the Lattice ECP5 fpga. There is also an OrangeCrab 25F. If you want to reproduce experiments in this repo, keep in mind that I'm using an OrangeCrab r0.2.1 85F.
This repository is structured as a lab notebook describing (hopefully) reproducible experiments with FPGA gateware and firmware. As such, there are files of different types, from different sources, and with different licenses.
In general, files in this repository mostly fit into four categories:
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My "MIT OR CC-BY-SA-4.0" stuff: lab notes that may include code snippets
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My "MIT" stuff: source code, documentation, build files, and prebuilt binaries for software, such as firmware to run on an RV32 CPU
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My "CERN-OHL-P-2.0", "ISC", or "Apache-2.0" stuff: source code, documentation, build files, and prebuilt binaries for hardware design specifications, such as pin constraint files and Verilog peripherals. For things that I write to extend a soft CPU that somebody else wrote, I try to match the original license.
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Other people's openly-licensed stuff: files copyrighted by people who are not me (e.g. prebuilt binaries that I built using MIT-licensed source code and build files from orangecrab-fpga/orangecrab-examples)
For specifics, check the individual files and folders.
My text files should have SPDX license identifier comments at the top (for markdown, view the raw files to see the HTML comments). Files that came from elsewhere should be grouped in a folder next to a LICENSE or README file that explains their origin and licensing.
For plain-text copies of the licenses used in this repo, refer to the LICENSES folder.