UART Transceiver in Verilog

This project implements a UART (Universal Asynchronous Receiver/Transmitter) transceiver using Verilog RTL. It includes both transmit (TX) and receive (RX) modules, a testbench for simulation, and FPGA deployment with 7-segment display verification.

🔧 Features

• UART Transmitter (TX) and Receiver (RX) modules
• Parameterized clock division for baud rate configuration
• Loopback test and data echo functionality
• Verilog testbench for simulation
• FPGA implementation and hardware validation