Support for Cheshire on Digilent Genesys 2 #252
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Couple minor things to fix then should be good to merge. |
Signed-off-by: Matt Rossouw <matthew.rossouw@unsw.edu.au> Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
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This PR adds support for the Cheshire SoC design implemented on the Digilent Genesys2 FPGA board.
Cheshire is an implementation of the CVA6 core, similarly to Ariane (#246).
This port depends upon seL4 support in this PR.