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loader: support spin table SMP booting#453

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Ivan-Velickovic wants to merge 1 commit intomainfrom
rpi4b_smp_fix
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loader: support spin table SMP booting#453
Ivan-Velickovic wants to merge 1 commit intomainfrom
rpi4b_smp_fix

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@Ivan-Velickovic
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@Ivan-Velickovic Ivan-Velickovic commented Mar 25, 2026

Pretty much every single ARM platform that we want to support uses PSCI for booting secondary cores, except for Raspberry Pi 4B which uses a spin-table mechanism.

TODO:

  • Fix release mode case where print lock is not used, have local patches but need to test.

Closes #401.

@Ivan-Velickovic Ivan-Velickovic force-pushed the rpi4b_smp_fix branch 2 times, most recently from 8d71a57 to 43567c3 Compare March 25, 2026 06:49

*release_addr = (uint64_t)arm_spin_table_secondary_cpu_entry_asm;
/* Ensure that the write to release address occurs before waking up the secondary CPU. */
asm volatile("dsb sy" ::: "memory");
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The dsb can also be explained using the following text from Arm ARM:

$\textsf{I}_\textsf{DVZXD}$ Arm recommends that software includes a DSB instruction before any SEV instruction. DSB instruction ensures that no instructions, including any SEV instructions, that appear in program order after the DSB instruction, can execute until the DSB instruction has completed

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I would also say "finishes" instead of "occurs", as that is more explicit.

(Cool, I couldn't figure out a way to do those subscripts for Arm references, now I know how.)

Comment on lines +19 to +28
* For the moment this code assumes that CPUs are booted using the ARM PSCI
* standard. We reference Version 1.3 issue F.b.
* Most of this code that CPUs are booted using the ARM PSCI standard.
* We reference Version 1.3 issue F.b.
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What are you trying to say here?

"For booting CPUs with PSCI we reference Verions 1.3 issue F.b of the Arm PSCI standard."?

But if you keep the "Most of this code assumes" bit, it would make more sense to have it at the top of the file.

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I messed this up, I've put at the top of the file and made it make sense now.


*release_addr = (uint64_t)arm_spin_table_secondary_cpu_entry_asm;
/* Ensure that the write to release address occurs before waking up the secondary CPU. */
asm volatile("dsb sy" ::: "memory");
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I would also say "finishes" instead of "occurs", as that is more explicit.

(Cool, I couldn't figure out a way to do those subscripts for Arm references, now I know how.)

Pretty much every single ARM platform that we want to support uses
PSCI for booting secondary cores, except for Raspberry Pi 4B which
uses a spin-table mechanism.

Signed-off-by: Ivan Velickovic <i.velickovic@unsw.edu.au>
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Rasberry Pi 4B regression since 2.1.0

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