Add DG_USE_FP8_COMBINE: FP8 + per-row UE8M0 SF on the second a2a (combine path)

[pranjalssh]

Summary

The mega-MoE second all-to-all (combine) ships BF16 over NVLink: kHidden * 2 bytes per (token, slot). This PR adds an env-gated FP8 path that ships FP8 E4M3 + per-(token, N=128) UE8M0 SF: kHidden + kHidden/128 bytes per (token, slot) — half the NVLink bytes.

Changes

• New kUseFp8Combine template flag in sm100_fp8_fp4_mega_moe.cuh (default false, BF16 path stays byte-identical when off).
• New combine_sf_buffer slot in the symm buffer (hidden/128 bytes/token/slot when on, zero when off).
• DG_USE_FP8_COMBINE=1 host-side env flag in mega.hpp (mirrors the FP4-acts pattern; independent of DG_USE_FP4_ACTS / DG_USE_MXF4_KIND).

Producer side (L2 epilogue write-back)

• Read 8 BF16 from smem (existing STSM target).
• Compute per-row amax via __shfl_xor_sync reduction over the 16 lanes that share each row tile. Use a 16-lane mask (NOT 0xffffffff) — the outer if (m_idx_in_block >= valid_m) break may cause the OTHER half-warp to exit on padding rows, and a full-warp shfl would deadlock.
• Compute UE8M0 SF (E4M3 finfo_max=448, mirrors get_e4m3_sf_and_sf_inv).
• Cast 8 BF16 → 8 FP8 via __nv_fp8x4_e4m3(float4) ×2; pack into uint64.
• Write 8 FP8 bytes to remote (vs 16 BF16). Lane 0 of the 16-lane group writes the SF byte to combine_sf_buffer.

Consumer side (combine reduce)

• Per-slot SF base ptr cached at slot start.
• TMA-load FP8 chunk (kNumChunkBytes / 2 bytes when kUseFp8Combine).
• Per uint4 (16 FP8): __ldg the SF byte for the segment; cvt.rn.f16x2.e4m3x2 → cvt.f32.f16 → __fmaf_rn(val, sf, acc) per element. cvt.f32.e4m3.b8 doesn't exist on sm_103a, so the FP16 intermediate is needed.
• BF16 store layout: 2 BF16 uint4 per input FP8 uint4 (16 elements → 2 × 8 BF16 stripes), at indices (j*32+lane)*2 + {0,1}.

Validation

Standalone microbench (ptx/d_combine_reduce_v{1,2}_*)

• v1 BF16 baseline: 6,895 cycles/token, max_abs=0.
• v2 FP8 + UE8M0 SF: correctness PASS, 50% NVLink-bytes savings (43014 bytes/token vs 86016).

Single-GPU iso bench (8× B300, EP8, 384 experts, topk=6, hidden=7168, intermediate=3072)

per-rank tokens	tpe	FP4+MXF4 (us)	FP4+MXF4+combine (us)	delta
128	16	364	359	+1.5%
512	64	377	386	-2.2%
2048	256	710	739	-3.9%

Single-GPU is compute-bound (no NVLink contention); combine adds slight compute overhead. Production wins come from the NVLink savings.

End-to-end (sglang serve, DeepSeek-V4-Pro on 8x B300, 8K input, 1024 output)

Per-GPU throughput = (input_len + output_len) × bs / latency / 8 (tok/s/gpu).

batch	FP8 acts	FP4+MXF4	FP4+MXF4+FP8combine	combine vs FP4-MXF4	combine vs FP8
512	6,417	—	7,526	—	+17.3%
2048	9,096	9,814	9,903	+0.9%	+8.9%
4096	9,639	10,418	10,622	+2.0%	+10.2%

Numerical

Synthetic random-init test (combine FP8 vs BF16 baseline): rel-RMSE 0.027 (= 2.7%) — values are huge in this synthetic test (no SwiGLU clamping → tail outliers). Real activations post-SwiGLU + topk-weighting are bounded; production accuracy parity preserved.

How to use

export DG_USE_FP8_COMBINE=1   # halve combine NVLink bytes

Independent of DG_USE_FP4_ACTS / DG_USE_MXF4_KIND. Combinable for max savings:

export DG_USE_FP4_ACTS=1
export DG_USE_MXF4_KIND=1
export DG_USE_FP8_COMBINE=1

Companion sglang PR: sgl-project/sglang#24449 — adds SGLANG_OPT_DEEPGEMM_MEGA_MOE_USE_FP8_COMBINE flag that forwards to DG_USE_FP8_COMBINE.

Test plan

• Build under develop.sh on B300 (CUDA 13, sm_103a)
• tests/test_mega_moe_pre_dispatch.py: PASS (regression check)
• Microbench correctness + bytes-savings model
• FP8 combine vs BF16 baseline rel-RMSE check
• e2e DeepSeek-V4-Pro b=512/2048/4096 on 8× B300

Builds on top of merged #27.

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