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History / Amiga port design

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  • Document Copperline testing path and -X serialdebug capture. Add a Copperline section to the testing guide: independent FPU-correct emulator used as the oracle that pinned the Amiberry NaN bug, its current FPU-instruction gap (Copperline#45), and serial->stdout capture via the port's new -X serialdebug option (RawPutChar). Note the Amiberry 68881 NaN-mangling caveat alongside the FPU variant. Mirror the summary into the design log's testing section. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 27, 2026
  • design log: record the asyncio execution-speed finding. Add a known-limitations entry: asyncio is enabled, but a few timing/ ordering tests (gather_notimpl, wait_for, fair) fail on the slow 68k because tasks get ph_key = ticks_ms() at create time and per-iteration overhead (~12-50ms on the emulated 68020) outlasts the tests' short sleeps, reordering output. Pass on unix; not a port bug; not timing precision (us-precise busy-wait WFE unchanged); eases on faster hardware. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 21, 2026
  • Amiga docs: Add test-status scoreboard; slim the testing page. New Amiga-port-test-status page is the at-a-glance scoreboard: all 31 port-local smoke tests grouped by area with vamos/Amiberry status, the upstream-suite per-directory snapshot, and the remaining real-hardware failures split into genuine gaps / environmental / won't-fix platform differences, plus a recently-fixed table. Testing page cleanup (1048 -> 945 lines): - Consolidated the two conflicting suite snapshots into one "Suite results" section pointing at the scoreboard for the breakdown; kept the FPCR-rounding and sys.path[0] fix write-ups. - Compressed the float/basics/extmod serial narratives to their conclusions, with the forensic detail tucked into <details> blocks. - Replaced the two duplicated known-failure tables with a pointer to the scoreboard, so failure status has one home. - Added a runbook-vs-scoreboard pointer at the top. Repointed the design log's known-failures link and the now-orphaned testing-page anchors at the scoreboard. Home.md lists the new page. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Amiga docs: Split the design log into per-phase wiki pages. Amiga-port-design.md shrinks from 2772 to 564 lines, becoming a lean index + architecture reference (overview, linked phase-status table, CPU/ABI, toolchain, NLR, GC, port layout, investigation items, known limitations, testing pointer). All per-phase log content moved out. New pages: Phase 12 (native emitter rework), 17 (library access), 18 (ARexx), 37 (datatypes, planned), 39 (extmod opt-ins); plus two era pages grouping the small foundational phases (0-11 Foundation, 13-27 Platform integration) to avoid stub pages. The 10 existing Phase-NN-*-plan pages (28-36, 38) absorb their design- log section as a "Design and rationale" block above the step plan, with Files/Status deduplicated. Every phase page gets a consistent H1 and a back-link to the design log; Home.md lists them all. Killed stale docs/phaseNN-*.md in-tree link targets and fixed a wrong Phase 17 link; verified zero dangling internal wiki links. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Amiga docs: viper long-shift fix (Phase 12c) — emitter complete. The remaining viper failures were one bug, not the predicted register allocator + missing pointer opcodes: asm68k.h emitted word-size shift opcodes (LSL.W/LSR.W, and ASR encoded as ASL), so any viper shift past bit 15 was wrong. Fixed to LSL.L/LSR.L/ASR.L, flipping 6 tests. micropython/ is now 85 pass / 18 skip / 5 fail; the 5 remaining are big-endian vs little-endian-.exp byte-order differences in the viper ptr16/ptr32 boundary tests, moved to the platform-differences table. The native + viper emitter is functionally complete. MAX_REGS_FOR_LOCAL_VARS=1 is a perf limit, not a correctness gap. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Amiga design log: Phase 12b done — native emitter complete. The native_const/closure/gen crashes were a big-endian byte-order bug: the emitter wrote prelude_ptr_index (and the generator start_offset) little-endian via mp_asm_base_data(), but the 68k reads it back as a native uintptr_t, so index 1 became 0x01000000 and child_table[] indexed out of bounds. Fixed by byte-swapping on N_68K. Mark Phase 12 done, rewrite 12b with the real root cause (the old A4 / ASM_CALL_IND theory was wrong — native->native calls already worked), and update the counts: micropython/ 79 pass / 18 skip / 11 fail, all 11 remaining are viper register/pointer gaps (zero native failures). Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Amiga testing: Record full micropython/ vamos re-run for Phase 12a. Replace the derived +3/-3 NLR estimate with the measured full-suite result: micropython/ is 76 pass / 18 skip / 14 fail (was 70/18/20), +6 pass / -6 fail with zero regressions. The register NLR also fixed viper_try/viper_with/viper_globals (NLR-only, no viper register work needed), so the viper bucket drops 14 -> 11 and native 6 -> 3. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Amiga design log: Phase 12a register NLR done; split out 12b. try/except/with in @micropython.native now work via the register-based 68k NLR (nlr68k.S + nlr68k_jump.c). Mark Phase 12a done, break the residual native-call/closure/generator crashes out as Phase 12b, and update the NLR architecture description, limitations tables, and the test-failure counts (native bucket 6 -> 3; micropython/ +3 pass). Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 20, 2026
  • Add investigation items for ClassAct and a header-to-Python tool. Two sized cost/benefit sketches under a new top-level "Investigation items" section (between Phase 39 and Other known limitations): - ClassAct / ReAction GUI binding: BOOPSI toolkit wrap to give the port a real windowed UI surface beyond Phase 30/31's modal requesters. Sketches API shape, ~30-class scope, layout-engine win, five open questions, two-phase split verdict. - Third-party header to drop-in Python constants tool (amiga-headergen): orchestrator over the existing fdgen / taggen / structgen engines emitting a single .py the user drops into PROGDIR:, removing the hand-translate-the-header pain for non-NDK libraries. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 16, 2026
  • Document the 2026-06-13 tooling and conformance pass. Adds a "Tooling and upstream-conformance pass" subsection to the design log covering: - New tools/amiga-structgen.py, completing the trio with fdgen and taggen so all three NDK-derived data tables (FDs, tag IDs, struct layouts) are now generated rather than transcribed. - MIT license header retrofit on 25 port-local C/H files plus three variant headers. - mphalport.h guard renamed from #pragma once to MICROPY_INCLUDED_*. - main.c uncrustify pass (two #if/#endif indents). - Commit policy realigned with upstream's DCO -- sign-off on every new commit, branch to be squashed before any merge attempt so the unsigned historical commits don't matter. Also adds a cross-reference from the "Other known limitations" section to the testing wiki's expanded TODO failure list, so the two pages don't drift. Signed-off-by: Simon Dick <simond@irrelevant.org>

    @sidick sidick committed Jun 13, 2026
  • Smoke test sweep: document new tests + asm68k MOVEQ fix.

    @sidick sidick committed Jun 2, 2026
  • Phase 39 step 4: btree (Berkeley DB) surface shipped.

    @sidick sidick committed Jun 2, 2026
  • Phase 39 step 3: deflate compress (write) surface shipped.

    @sidick sidick committed Jun 2, 2026
  • Phase 39 step 2: hashlib MD5 + SHA-1 shipped.

    @sidick sidick committed Jun 2, 2026
  • Phase 39 step 1: Wall-clock time surface shipped.

    @sidick sidick committed Jun 2, 2026
  • Phase 38: Add Status -- done blocks to design log and step plan.

    @sidick sidick committed Jun 2, 2026
  • Import Amiga port design log and per-phase plans from in-tree docs/.

    @sidick sidick committed Jun 2, 2026