Correct AmiSSL #111 framing: it was CPU speed, not a bug
The filed AmiSSL issue turned out to be a processor-speed limitation,
not an AmiSSL defect. Drop the bug-tracker link and state the resolution
plainly on both pages.
Amiga docs: Split the design log into per-phase wiki pages.
Amiga-port-design.md shrinks from 2772 to 564 lines, becoming a lean
index + architecture reference (overview, linked phase-status table,
CPU/ABI, toolchain, NLR, GC, port layout, investigation items, known
limitations, testing pointer). All per-phase log content moved out.
New pages: Phase 12 (native emitter rework), 17 (library access), 18
(ARexx), 37 (datatypes, planned), 39 (extmod opt-ins); plus two era
pages grouping the small foundational phases (0-11 Foundation, 13-27
Platform integration) to avoid stub pages.
The 10 existing Phase-NN-*-plan pages (28-36, 38) absorb their design-
log section as a "Design and rationale" block above the step plan, with
Files/Status deduplicated. Every phase page gets a consistent H1 and a
back-link to the design log; Home.md lists them all.
Killed stale docs/phaseNN-*.md in-tree link targets and fixed a wrong
Phase 17 link; verified zero dangling internal wiki links.
Signed-off-by: Simon Dick <simond@irrelevant.org>
Refresh Phase 28 / 29 pages with latest in-tree updates.
Import Amiga port design log and per-phase plans from in-tree docs/.