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TG-641: eth1 10g copper port not recover after down up#85

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paul-sirin merged 2 commits into
tg-v6.18-ath12k-nextfrom
bugfix/TG-641-10g-copper-not-recover-down-up
May 15, 2026
Merged

TG-641: eth1 10g copper port not recover after down up#85
paul-sirin merged 2 commits into
tg-v6.18-ath12k-nextfrom
bugfix/TG-641-10g-copper-not-recover-down-up

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@paul-sirin paul-sirin commented May 14, 2026

This PR contains fixes for 2 issues in 88x3310 PHY driver:

  1. it needs 10ms delay between power up and SWRST on resume
  2. it should persist default initial 10BASER serdes on resume

Comment thread drivers/net/phy/marvell10g.c
Comment thread drivers/net/phy/marvell10g.c Outdated
Comment thread drivers/net/phy/marvell10g.c Outdated
Comment thread drivers/net/phy/marvell10g.c Outdated
Comment thread drivers/net/phy/marvell10g.c
Comment thread drivers/net/phy/marvell10g.c Outdated
@paul-sirin paul-sirin force-pushed the bugfix/TG-641-10g-copper-not-recover-down-up branch 3 times, most recently from f6ff7b4 to e9ea55f Compare May 15, 2026 12:34
@paul-sirin paul-sirin marked this pull request as ready for review May 15, 2026 13:16
…TG-641)

On 88X3310 with PTP enabled, TX and RX stop working from the second ip link set
up onwards. The root cause is a race in mv3310_power_up(): the function issues
a software reset (SWRST, MV_V2_PORT_CTRL bit 15) followed by msleep(100), but
when resume is called again before the previous SWRST has fully completed, the
new SWRST is issued while bit 15 is still asserted by the PHY. This corrupts
the reset sequence and leaves the data path in a broken state.

Fix this by polling MV_V2_PORT_CTRL bit 15 before issuing SWRST, waiting up to
200ms for the PHY to signal it is ready for a new reset (bit 15 = 0). Profiling
showed that in normal operation the wait is under 10ms, but occasionally
reaches ~157ms. If the poll times out, a warning is emitted and execution
continues rather than aborting the power-up sequence.

This is only applied to 88X3310 with firmware >= 0.3.0.0, matching the existing
guard for the SWRST
…e (TG-641)

Issue caused TX/RX to fail on the second and subsequent ip-link-down/up
cycles on an 88X3310 PHY paired with an mvpp2 MAC configured for
10GBASE-R: wrong MACTYPE mode in config_init.  mv3310_config_init forced
MACTYPE to 10GBASER (XFI/SGMII auto-neg). In auto-neg mode the PHY
switches its host-side serdes to SGMII at 1G link speed, which causes
phylink to invoke mac_prepare/mac_config with a changed interface, which
in turn causes mvpp2 to reinitialise the comphy from 10GBASE-R to SGMII.
Since the 88X3310 always presents a fixed 10GBASE-R (XFI) serdes toward
the MAC, the comphy reconfiguration corrupts the link and RX stays
broken.

Fix: always select RATE_MATCH mode (MACTYPE 6). In this mode the PHY
presents a fixed 10GBASE-R serdes to the MAC and adapts the copper rate
internally, so the MAC/comphy never needs reconfiguring across speed
changes.

Add a copper_multispeed flag to mv3310_mactype so that RATE_MATCH
entries still expose SGMII/2.5G/5G in possible_interfaces, allowing
phylink to validate and announce all copper speeds to user space.
@paul-sirin paul-sirin force-pushed the bugfix/TG-641-10g-copper-not-recover-down-up branch from e9ea55f to e9cf2db Compare May 15, 2026 19:24
@paul-sirin paul-sirin merged commit cbeb13d into tg-v6.18-ath12k-next May 15, 2026
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2 participants