Verilog Syntax Issues Resolved

auto_generated/netlist_files/all_clocks_netlist.v

@@ -0,0 +1,19 @@
+/*
+Command: all_clocks
+Description:
+    -Returns a list of all defined clocks
+
+SDC Example:
+    all_clocks
+*/
+
+module all_clocks(
+    input wire clk1,
+    input wire clk2,
+    input wire D,
+    output reg Q
+);
+    always @(posedge clk1) begin
+        Q <= D;
+    end
+endmodule

auto_generated/netlist_files/set_clock_uncertainty_netlist.v

@@ -19,7 +19,7 @@ module set_clock_uncertainty(
 );
     //Simple CDC for inter-clock uncertainty
     //Internal data from clk1 to clk2
-    wire data_internal;
+    reg data_internal;
 
     always @(posedge clk1) begin
         data_internal <= port1;
@@ -41,12 +41,6 @@ module set_clock_uncertainty(
     //Instance to create pin inputs (ff_pin/pin1 and ff_pin/pin2)
     wire ff_pin_out;
     module_pin ff_pin(.clk(clk1), .pin1(clk1), .pin2(clk2), .out(ff_pin_out));
-
-    //Dummy logic
-    always @(posedge clk1) begin
-        out <= port1 & port2
-    end
-
 endmodule
 
 //Module defining pins

auto_generated/netlist_files/set_disable_timing_netlist.v

@@ -0,0 +1,22 @@
+/*
+Command: set_disable_timing
+Description:
+    -Disables timing through paths specified by the command
+
+
+SDC Example:
+    set_disable_timing -from 
+    set_disable_timing 
+*/
+
+//Main module
+module set_disable_timing(
+    input wire clk1,
+    input wire D, 
+    output reg Q
+);
+    always @(posedge clk1) begin
+        Q <= D;
+    end
+
+endmodule

auto_generated/netlist_files/set_false_path_netlist.v

@@ -46,7 +46,7 @@ module inst2(
     output reg net2_out
 );
     always @(posedge clk2) begin
-        pin2 <= net1_in
-        net2_out <= ~net1_in
+        pin2 <= net1_in;
+        net2_out <= ~net1_in;
     end
 endmodule

auto_generated/netlist_files/set_max_delay_netlist.v

@@ -46,7 +46,7 @@ module inst2(
     output reg net2_out
 );
     always @(posedge clk2) begin
-        pin2 <= net1_in
-        net2_out <= ~net1_in
+        pin2 <= net1_in;
+        net2_out <= ~net1_in;
     end
 endmodule

auto_generated/netlist_files/set_min_delay_netlist.v

@@ -46,7 +46,7 @@ module inst2(
     output reg net2_out
 );
     always @(posedge clk2) begin
-        pin2 <= net1_in
-        net2_out <= ~net1_in
+        pin2 <= net1_in;
+        net2_out <= ~net1_in;
     end
 endmodule

auto_generated/netlist_files/set_multicycle_path_netlist.v

@@ -46,7 +46,7 @@ module inst2(
     output reg net2_out
 );
     always @(posedge clk2) begin
-        pin2 <= net1_in
-        net2_out <= ~net1_in
+        pin2 <= net1_in;
+        net2_out <= ~net1_in;
     end
 endmodule

auto_generated/netlist_files/set_output_delay_netlist.v

@@ -18,7 +18,7 @@ module set_output_delay (
 
     //Instance to create 'ref_pin' (ff_ref/clk)
     wire ff_ref_q;
-    FF ff_ref (.clk(src_clk), .D(data_in), .Q(ff_ref_q));
+    FF_ref ff_ref (.clk(src_clk), .D(data_in), .Q(ff_ref_q));
 
     //Instance to create pin outputs(ff_pin/pin1 and ff_pin/pin2)
     wire ff_pin_pin1;