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@Minchan-Kwon Minchan-Kwon commented Dec 12, 2025

Added the images describing the benchmark suite

Summary by CodeRabbit

  • New Features

    • Added a module exposing multiple independent clocks for toggling/monitoring.
    • Added a dual-channel data-capture module that outputs a 2-bit combined signal (one channel captures inverted input).
    • Added an arithmetic/aggregation module with reset, valid gating, and a ready indicator.
  • Chores

    • SDC generation tool simplified: fewer optional flags, deterministic pattern inclusion, and automatic clock prerequisites.
  • Documentation

    • Added an auto-generated benchmark README and updated SDC syntax docs with an illustrative image.

✏️ Tip: You can customize this high-level summary in your review settings.

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coderabbitai bot commented Dec 12, 2025

Walkthrough

Adds three auto-generated Verilog netlist modules (get_clocks, get_pins, get_ports), updates the SDC-generation script to always include object patterns and prepend create_clock prerequisites, and adds an auto_generated README plus a small docs image addition.

Changes

Cohort / File(s) Summary
New Verilog netlist modules
auto_generated/netlist_files/get_clocks_netlist.v, auto_generated/netlist_files/get_pins_netlist.v, auto_generated/netlist_files/get_ports_netlist.v
Added get_clocks (inputs: clk1, clk2, clk_gen, clock; output reg dummy_out toggles on any posedge), get_pins + DFF (two single-bit DFFs instantiated; data_out is 2-bit reg concatenation), and get_ports (ports: clk, rst, data1_in, data2_in, valid_in; result_out is reg updated when valid_in, ready_out is constant wire).
SDC generation script
scripts/generate_sdc.py
Removed optional flags (-filter, -of_objects, related branching); PATTERNS updated; generators for clocks/ports/pins now always append deterministic patterns and prefix commands with create_clock prerequisite lines.
Documentation additions
auto_generated/README.md, docs/syntax/README.md
Added an auto-generated README describing the benchmark suite and an image reference in the SDC syntax docs.

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

  • Areas needing extra attention:
    • scripts/generate_sdc.py — ensure pattern composition, flag handling changes, and correct create_clock prefixing.
    • auto_generated/netlist_files/get_pins_netlist.v — DFF instantiation, signal directions/bit ordering, and EOF newline.
    • auto_generated/netlist_files/get_ports_netlist.v — reset semantics, valid gating, and signal widths.
    • auto_generated/netlist_files/get_clocks_netlist.v — multi-clock posedge sensitivity and reg output update semantics.

Suggested reviewers

  • AlexandreSinger

Poem

🐇 I hopped through nets where clock seeds sprout,
I nudged two DFFs and traced the route,
Patterns sewn and scripts refined—
small modules formed, tidy and kind. 🥕

Pre-merge checks and finishing touches

❌ Failed checks (1 warning)
Check name Status Explanation Resolution
Title check ⚠️ Warning The PR title mentions adding an image description, but the actual changes include three new Verilog netlist modules, significant script modifications, and a README—far beyond just documentation images. Revise the title to accurately reflect all major changes, such as 'Add netlist modules, update SDC generation logic, and add benchmark documentation' or focus on the primary change if one is intended.
✅ Passed checks (2 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Docstring Coverage ✅ Passed Docstring coverage is 100.00% which is sufficient. The required threshold is 80.00%.
✨ Finishing touches
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Post copyable unit tests in a comment

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Actionable comments posted: 4

🧹 Nitpick comments (1)
auto_generated/netlist_files/get_pins_netlist.v (1)

1-35: Verify file completeness.

The file appears to be missing a final newline at the end. While not a critical issue, it's a common best practice to end source files with a newline character.

📜 Review details

Configuration used: CodeRabbit UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 1041d08 and a64eeea.

⛔ Files ignored due to path filters (3)
  • docs/images/Synopsys-Design-Constraints.png is excluded by !**/*.png
  • docs/images/Syntax-Suite.png is excluded by !**/*.png
  • docs/images/Timing-Suite.png is excluded by !**/*.png
📒 Files selected for processing (3)
  • auto_generated/netlist_files/get_clocks_netlist.v (1 hunks)
  • auto_generated/netlist_files/get_pins_netlist.v (1 hunks)
  • auto_generated/netlist_files/get_ports_netlist.v (1 hunks)

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Actionable comments posted: 1

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)
scripts/generate_sdc.py (1)

314-352: generate_get_pins: you’re iterating unused options → duplicate outputs and wasted generation

After the change, only -regexp/-nocase/-quiet are actually appended, but the loop still enumerates combinations over ["-hierarchical", "-hsc", "-filter", ...] (Line 321). That will generate many identical commands and file duplicates. Tighten optional_options (and update the docstring) to match what’s emitted.

 def generate_get_pins():
     '''
-    Required:
-    Optional: -hierarchical, -hsc, -filter, -regexp, -nocase(Valid only with -regexp), -quiet, -of_objects, patterns
-    Note: -hierarchical cannot be used with -of_objects
+    Optional: -regexp, -nocase (legal only with -regexp), -quiet
     '''
     commands = [] #List containing all possible combinations of options
-    optional_options = ["-hierarchical", "-hsc", "-filter", "-regexp", "-nocase", "-quiet", "-of_objects", "patterns"]
+    optional_options = ["-regexp", "-nocase", "-quiet"]
🧹 Nitpick comments (2)
scripts/generate_sdc.py (2)

236-273: generate_get_ports: consider dropping the create_clock prerequisite and/or align pattern to -regexp

get_ports generally doesn’t require clocks to exist; prefixing create_clock may be harmless but can add noise and (if the referenced port doesn’t exist) introduce avoidable tool errors in suites that only want to validate get_ports. Also, if -regexp is present, ensure pattern is a regex (not a glob-ish token like *in).

-            #Add create_clock prerequisites
-            pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces)
+            # If you truly need prerequisites here, consider referencing a port that always exists
+            # in the benchmark netlist, or omit prerequisites for get_ports entirely.
+            # pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces)
-            pattern = generate_pattern("port")
+            pattern = generate_pattern("port")  # consider generate_pattern("port_regex") when -regexp is set
             pieces.append(pattern)

274-313: generate_get_clocks: prereq clocks should be conditional on the chosen clock pattern

You always create 4 clocks (clk1/clk2/clk_gen/clock) even if the generated get_clocks pattern targets something else; this can create unnecessary constraints and failures if some ports don’t exist in a given netlist. Consider emitting prerequisites only for the clocks implied by the pattern (or ensure the netlists always define these ports).

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Reviewing files that changed from the base of the PR and between a64eeea and f2205ca.

📒 Files selected for processing (1)
  • scripts/generate_sdc.py (5 hunks)

Comment on lines +103 to 108
"clock": ["clk*", "clk_gen", "clock", "clk1"],
"port": ["data*", "*in", "*out", "valid_in"],
"pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
"cell": ["inst*", "reg_*", "*_buffer"],
"net": ["net*", "n[0-9]*", "*_data"]
}
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⚠️ Potential issue | 🟠 Major

Ensure patterns match the selected mode (glob vs -regexp)

PATTERNS now feeds both plain mode and -regexp mode. Several entries (e.g., clk*, *in, */Q) look like glob patterns; under -regexp they may be invalid or at least semantically different than intended depending on the SDC implementation. Consider maintaining separate pattern banks (glob vs regex) or translating when -regexp is present.

 PATTERNS = {
-    "clock": ["clk*", "clk_gen", "clock", "clk1"],
-    "port": ["data*", "*in", "*out", "valid_in"],
-    "pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
+    # Consider splitting into "glob" vs "regex" banks if -regexp is used.
+    "clock": ["clk*", "clk_gen", "clock", "clk1"],
+    "port": ["data*", "*in", "*out", "valid_in"],
+    "pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
     "cell": ["inst*", "reg_*", "*_buffer"],
     "net": ["net*", "n[0-9]*", "*_data"]
     }
📝 Committable suggestion

‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
"clock": ["clk*", "clk_gen", "clock", "clk1"],
"port": ["data*", "*in", "*out", "valid_in"],
"pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
"cell": ["inst*", "reg_*", "*_buffer"],
"net": ["net*", "n[0-9]*", "*_data"]
}
PATTERNS = {
# Consider splitting into "glob" vs "regex" banks if -regexp is used.
"clock": ["clk*", "clk_gen", "clock", "clk1"],
"port": ["data*", "*in", "*out", "valid_in"],
"pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
"cell": ["inst*", "reg_*", "*_buffer"],
"net": ["net*", "n[0-9]*", "*_data"]
}
🤖 Prompt for AI Agents
In scripts/generate_sdc.py around lines 103 to 108, PATTERNS currently contains
glob-style entries that are being used regardless of whether the SDC engine is
invoked in plain (glob) or -regexp mode; this can produce incorrect or invalid
matches. Fix by branching on the selected mode: if mode == "regexp" either (a)
maintain a separate PATTERNS_REGEXP mapping with proper regular expressions for
each key, or (b) programmatically translate glob patterns to equivalent regex
(escaping as needed and converting * -> .* and ? -> .) before emitting them;
validate converted patterns (e.g., compile them) and use the appropriate bank
when generating the SDC output.

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Coderabbit is correct here @Minchan-Kwon . All of the examples I see here are Glob, not regex. For now, I think its ok to just support Glob. If you want to support Regex, you would need some slightly different examples.

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Seems like the humans are having a chat. I'll hop back into my burrow for now. If you need me again, just tag @coderabbitai in a new comment, and I'll come hopping out!

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Looks great @Minchan-Kwon

A couple of comments.

Comment on lines +103 to 108
"clock": ["clk*", "clk_gen", "clock", "clk1"],
"port": ["data*", "*in", "*out", "valid_in"],
"pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
"cell": ["inst*", "reg_*", "*_buffer"],
"net": ["net*", "n[0-9]*", "*_data"]
}
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Coderabbit is correct here @Minchan-Kwon . All of the examples I see here are Glob, not regex. For now, I think its ok to just support Glob. If you want to support Regex, you would need some slightly different examples.

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I like this picture a lot. Can you please add a reference to it in the syntax document that I wrote. You can add images to the README. I think this belongs at the top of that page as a summary.

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I like this image as well, but it may not fit with the Syntax docs. You could add your own README in the autogen suite for this if you would like.

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Same with this one. Normally, I like to always have the images in documentation somewhere so they are easier to access.

@Minchan-Kwon Minchan-Kwon marked this pull request as draft December 14, 2025 19:34
@Minchan-Kwon Minchan-Kwon marked this pull request as ready for review December 16, 2025 18:58
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Actionable comments posted: 2

🧹 Nitpick comments (2)
auto_generated/README.md (2)

1-1: Capitalize and hyphenate the title.

Line 1 should follow standard capitalization conventions for hyphenated compound adjectives.

-# Auto Generated Suite
+# Auto-Generated Suite

9-9: Simplify the phrasing for conciseness.

Consider removing the redundant "of" to streamline the text.

-All of the SDCs in this suite have been generated using generate_sdc.py included in the repository.
+All the SDCs in this suite have been generated using generate_sdc.py included in the repository.
📜 Review details

Configuration used: CodeRabbit UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between bf0920b and a41818f.

⛔ Files ignored due to path filters (3)
  • auto_generated/images/Syntax-Suite.png is excluded by !**/*.png
  • auto_generated/images/Timing-Suite.png is excluded by !**/*.png
  • docs/images/Synopsys-Design-Constraints.png is excluded by !**/*.png
📒 Files selected for processing (2)
  • auto_generated/README.md (1 hunks)
  • docs/syntax/README.md (1 hunks)
✅ Files skipped from review due to trivial changes (1)
  • docs/syntax/README.md
🧰 Additional context used
🪛 LanguageTool
auto_generated/README.md

[grammar] ~1-~1: Use a hyphen to join words.
Context: # Auto Generated Suite This is a benchmark sui...

(QB_NEW_EN_HYPHEN)


[style] ~8-~8: Consider removing “of” to be more concise
Context: ...uto_generated/images/Syntax-Suite.png) All of the SDCs in this suite have been generated ...

(ALL_OF_THE)

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Actionable comments posted: 0

♻️ Duplicate comments (1)
auto_generated/README.md (1)

7-7: Use descriptive alt text instead of the filename.

The alt text should be descriptive of the image content, not the filename. This ensures better accessibility and clarity.

-![Syntax-Suite.png](./images/Syntax-Suite.png)
+![Syntax Suite Benchmark Overview](./images/Syntax-Suite.png)
🧹 Nitpick comments (2)
auto_generated/README.md (2)

1-1: Use a hyphen to join compound adjective.

"Auto Generated" should be hyphenated as "Auto-Generated" when used as a modifier before the noun.

-# Auto Generated Suite
+# Auto-Generated Suite

9-9: Simplify "All of the" to "All the" for conciseness.

-All of the SDCs in this suite have been generated using generate_sdc.py included in the repository.
+All the SDCs in this suite have been generated using generate_sdc.py included in the repository.
📜 Review details

Configuration used: defaults

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between a41818f and 37007a7.

📒 Files selected for processing (1)
  • auto_generated/README.md (1 hunks)
🧰 Additional context used
🪛 LanguageTool
auto_generated/README.md

[grammar] ~1-~1: Use a hyphen to join words.
Context: # Auto Generated Suite This is a benchmark sui...

(QB_NEW_EN_HYPHEN)


[style] ~8-~8: Consider removing “of” to be more concise
Context: ...-Suite.png](./images/Syntax-Suite.png) All of the SDCs in this suite have been generated ...

(ALL_OF_THE)

🔇 Additional comments (1)
auto_generated/README.md (1)

5-5: Path correction acknowledged.

The relative path to the syntax documentation has been properly corrected from ./docs/syntax/README.md to ../docs/syntax/README.md.

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