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A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

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Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
Test_Program		Test_Program
Verilog_Files		Verilog_Files
Dual Core.gif		Dual Core.gif
README.md		README.md

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Dual-Core-RISC-V-Processor

A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

Dual Core Extension for (https://github.com/elec-tra/RISC_V_Processor)

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Mandelbrot program running on a Dual core RISC-V processor

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A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

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Verilog 96.0%
Assembly 4.0%