Add Verification and Regression Tests for base/ and axi/

[bengineerd]

Description

Add the Phase-1 SURF RTL regression baseline for the simulator-friendly base/, axi/, and initial dsp/ modules using the project’s Python-first flow (pytest + cocotb + GHDL + ruckus). This PR adds subsystem-organized cocotb regressions, checked-in IP-integrator wrappers where flat AXI/AXI-Lite/AXIS interfaces are needed, shared regression utilities, and updated planning/progress artifacts under docs/_meta/ so rollout state is recoverable without re-discovery. It also updates CI and local setup so the new regression tiers run reliably in parallel while legacy top-level benches still run in a separate serial pass.

Details

This branch validates the current axi-first Phase-1 queue through the final simulator-friendly axi/ modules and expands base/ coverage across FIFO, sync, delay, RAM, CRC, and general utility blocks, with the first dsp/ leaf now included. It also standardizes common GHDL compile flags, cocotb module discovery helpers, pytest parallel defaults, and the generated RTL queue artifacts used by the planning docs.

Existing Tests

The pre-existing cocotb tests were all folded into the new test structure.
In some cases they were re-written from VHDL driven testbenchs to cocotb.

Known expected-open items on this branch remain:

• tests/axi/axi4/test_AxiResize.py for the restored 32-bit -> 64-bit upsize case
• tests/axi/dma/test_AxiStreamDmaV2Read.py due to the current internal CONV_INTEGER assertion under GHDL

[Copilot]

Pull request overview

Adds a Phase-1 simulator-friendly SURF regression baseline using pytest + cocotb + GHDL + ruckus, with subsystem-organized test structure and checked-in thin VHDL wrappers to expose flat interfaces needed by cocotb.

Changes:

• Adds new cocotb/pytest regressions for AXI-Lite and AXI4 modules (plus initial protocol/base wrappers to support further tests).
• Introduces multiple IP-integrator / “flat” VHDL wrappers to bridge SURF record-based interfaces to cocotb-friendly flat ports.
• Updates local setup + CI + GHDL flag plumbing to run the new parallel regression tiers reliably.

Reviewed changes

Copilot reviewed 120 out of 295 changed files in this pull request and generated 9 comments.

Show a summary per file

File	Description
tests/axi/axi_lite/test_AxiLiteFifoPushPop.py	New AXI-Lite FIFO combined pop/loop/push regression
tests/axi/axi_lite/test_AxiLiteFifoPush.py	New AXI-Lite FIFO push-path regression
tests/axi/axi_lite/test_AxiLiteFifoPop.py	New AXI-Lite FIFO pop + loop regression
tests/axi/axi_lite/init.py	Marks AXI-Lite test package + brief module docstring
tests/axi/axi4/test_AxiWritePathFifo.py	New AXI4 write-path FIFO regression against AXI RAM model
tests/axi/axi4/test_AxiWriteEmulate.py	New AXI4 write-emulation regression (manual burst driving)
tests/axi/axi4/test_AxiRingBuffer.py	New AXI ring buffer regression using AXI RAM + AXIS sink
tests/axi/axi4/test_AxiResize.py	New AXI resize regression with parameter sweep + xfail upsize case
tests/axi/axi4/test_AxiReadPathFifo.py	New AXI4 read-path FIFO regression against AXI RAM model
tests/axi/axi4/test_AxiReadEmulate.py	New AXI4 read-emulation regression (manual burst driving)
tests/axi/axi4/test_AxiRam.py	New AXI RAM regression (burst + sparse overwrite)
tests/axi/axi4/test_AxiMonAxiL.py	New AXI monitor AXI-Lite surface/register regression
tests/axi/axi4/test_AxiMemTester.py	New AXI mem tester regression (AXI RAM + AXI-Lite status)
tests/axi/axi4/init.py	Marks AXI4 test package
tests/axi/init.py	Marks AXI subsystem test package + docstring
tests/init.py	Marks tests as a package for shared utilities/imports
tests/README.md	Documents subsystem-organized regression layout/policy
scripts/setup_regression_env.sh	Adds local bootstrap script for venv + ruckus + pytest commands
pytest.ini	Excludes tests/legacy from default collection
protocols/ssi/wrappers/SsiPrbsWrapper.vhd	Adds cocotb-facing SSI PRBS loopback wrapper
protocols/line-codes/wrappers/LineCode8b10bWrapper.vhd	Adds cocotb-facing 8b10b encode/decode wrapper
protocols/line-codes/wrappers/LineCode12b14bWrapper.vhd	Adds cocotb-facing 12b14b encode/decode wrapper
protocols/line-codes/wrappers/LineCode10b12bWrapper.vhd	Adds cocotb-facing 10b12b encode/decode wrapper
protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd	Adds cocotb-facing Hamming ECC wrapper with error injection mask
conda.yml	Adds a conda env recipe for the Python/GHDL cocotb flow
base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd	Flattens counter array output for cocotb inspection
base/sync/wrappers/SyncTrigRateWrapper.vhd	Cocotb wrapper mapping integer generics to real-valued DUT generics
base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd	Flattens per-lane trig-rate array to an slv for cocotb
base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd	Flattens SyncStatusVector counter array to an slv
base/sync/wrappers/SyncClockFreqWrapper.vhd	Cocotb wrapper mapping integer generics to real-valued clock monitor generics
base/general/wrappers/HeartbeatWrapper.vhd	Cocotb wrapper mapping integer period to real-valued Heartbeat generics
base/general/wrappers/DebouncerWrapper.vhd	Cocotb wrapper mapping integer debounce window to real-valued DUT period
base/fifo/wrappers/FwftCntWrapper.vhd	Cocotb-facing FWFT FIFO count wrapper (inferred/distributed variants)
base/crc/wrappers/Crc32PolyWrapper.vhd	Cocotb wrapper enabling integer override of CRC polynomial under GHDL
axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd	Adjusts pointer arithmetic to avoid range issues in narrower wrappers
axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd	Adds narrow AXI-Lite shim wrapper for AxiStreamDma
axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd	Adds narrow AXI-Lite shim wrapper for AxiStreamDmaFifo
axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd	Adds IP integrator wrapper for SlvArraytoAxiLite
axi/bridge/ip_integrator/IpBusToAxiLiteIpIntegrator.vhd	Adds IP integrator wrapper for IpBusToAxiLite
axi/bridge/ip_integrator/AxiLiteToIpBusIpIntegrator.vhd	Adds IP integrator wrapper for AxiLiteToIpBus
axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd	Adds IP integrator wrapper for AxiLiteToDrp
axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd	Adds flat AXI4 shim wrapper for AxiWriteEmulate
axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd	Adds flat AXI4 shim wrapper for AxiReadEmulate
axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd	Adds IP integrator wrapper for AxiMonAxiL
axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd	Adds wrapper exposing genTKeep for cocotb checks
axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd	Adds flat AXIS wrapper for TrailerRemove
axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd	Adds flat AXIS wrapper for Shift
axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd	Adds flat AXIS wrapper for Resize with sideband
axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd	Adds flat AXIS wrapper for PRBS flow control
axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd	Adds flat AXIS wrapper for Pipeline with sideband
axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd	Adds flat AXIS wrapper for Stream monitor outputs
axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd	Adds flat AXIS wrapper for GearboxUnpack
axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd	Adds flat AXIS wrapper for GearboxPack
axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd	Adds flat AXIS wrapper for Flush
axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd	Adds flat AXIS wrapper for Compact
axi/axi-lite/ip_integrator/AxiLiteSlaveIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteSlave req/ack interface
axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteRingBuffer
axi/axi-lite/ip_integrator/AxiLiteRespTimerIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteRespTimer
axi/axi-lite/ip_integrator/AxiLiteRegsIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteRegs
axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteRamSyncStatusVector
axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteMaster req/ack interface
axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd	Adds flat AXI-Lite wrapper for AxiLiteFifoPush (single-lane flattening)
Makefile	Centralizes GHDL flags and conditionally disables unsupported warnings
.github/workflows/surf_ci.yml	Updates CI to run new parallel regression tiers + adds concurrency controls

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