Complete tutorial code.

A tool for synthesizing Verilog programs

Testing processors with Random Instruction Generation

AXI interface modules for Cocotb

Comprehensive simulation environment for SystemVerilog RTL using CocoTB + PyUVM and opensource simulators.

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

cocotb: Python-based chip (RTL) verification

Structured UVM Course