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Kill break warnings #1015

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25013d4
remove use of "tmpreg"
Bob-the-Kuhn Mar 26, 2020
e1a500f
cleanup 9exta space, remove no longer needed "#if defined(TIM_IP_V2_1…
Bob-the-Kuhn Mar 26, 2020
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6 changes: 2 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -371,23 +371,21 @@ void SystemCoreClockUpdate (void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */

/* Enable FSMC clock */
RCC->AHBENR = 0x00000114U;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);

(void)(tmpreg);

/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
Expand Down
10 changes: 3 additions & 7 deletions system/Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -269,16 +269,14 @@ void SystemCoreClockUpdate (void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg = 0;

/* Flash 1 wait state */
FLASH->ACR |= FLASH_ACR_LATENCY;

/* Power enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);

/* Select the Voltage Range 1 (1.8 V) */
PWR->CR = PWR_CR_VOS_0;
Expand Down Expand Up @@ -312,7 +310,7 @@ void SystemInit_ExtMemCtl(void)
RCC->AHBENR = 0x000080D8;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);

/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CC00CC;
Expand Down Expand Up @@ -367,9 +365,7 @@ void SystemInit_ExtMemCtl(void)
RCC->AHBENR = 0x400080D8;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

(void)(tmpreg);
READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

/* Configure and enable Bank1_SRAM3 */
FSMC_Bank1->BTCR[4] = 0x00001011;
Expand Down
12 changes: 3 additions & 9 deletions system/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2765,11 +2765,9 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2782,11 +2780,9 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2802,11 +2798,9 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
__IO uint32_t tmpreg;
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand Down
12 changes: 3 additions & 9 deletions system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2697,11 +2697,9 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2714,11 +2712,9 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2734,11 +2730,9 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
__IO uint32_t tmpreg;
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand Down
12 changes: 3 additions & 9 deletions system/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_tim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2786,11 +2786,9 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2803,11 +2801,9 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2823,11 +2819,9 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
__IO uint32_t tmpreg;
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand Down
36 changes: 6 additions & 30 deletions system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3504,14 +3504,10 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand All @@ -3525,14 +3521,10 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand Down Expand Up @@ -3569,14 +3561,10 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
uint32_t BreakFilter)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand All @@ -3594,14 +3582,10 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand All @@ -3617,14 +3601,10 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
*/
__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand All @@ -3638,14 +3618,10 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
{
#if defined(TIM_IP_V2_1)
__IO uint32_t tmpreg;
#endif /* TIM_IP_V2_1 */
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
#if defined(TIM_IP_V2_1)
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
#endif /* TIM_IP_V2_1 */
}

Expand Down
12 changes: 3 additions & 9 deletions system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2790,11 +2790,9 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2807,11 +2805,9 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand All @@ -2827,11 +2823,9 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
__IO uint32_t tmpreg;
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
READ_REG(TIMx->BDTR);
}

/**
Expand Down
6 changes: 2 additions & 4 deletions system/STM32F1xx/system_stm32f1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -364,23 +364,21 @@ void SystemCoreClockUpdate (void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */

/* Enable FSMC clock */
RCC->AHBENR = 0x00000114U;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);

(void)(tmpreg);

/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
Expand Down
9 changes: 3 additions & 6 deletions system/STM32L1xx/system_stm32l1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -262,16 +262,14 @@ void SystemCoreClockUpdate (void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg = 0;

/* Flash 1 wait state */
FLASH->ACR |= FLASH_ACR_LATENCY;

/* Power enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);

/* Select the Voltage Range 1 (1.8 V) */
PWR->CR = PWR_CR_VOS_0;
Expand Down Expand Up @@ -305,7 +303,7 @@ void SystemInit_ExtMemCtl(void)
RCC->AHBENR = 0x000080D8;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);

/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00CC00CC;
Expand Down Expand Up @@ -360,9 +358,8 @@ void SystemInit_ExtMemCtl(void)
RCC->AHBENR = 0x400080D8;

/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

(void)(tmpreg);

/* Configure and enable Bank1_SRAM3 */
FSMC_Bank1->BTCR[4] = 0x00001011;
Expand Down