v2.10.0 — Shift module + Phase fixes

New module

Shift — 4-output CV shift register with per-output controls.

Each lane has its own:

• N pot (1–16): in parallel mode, the depth of the delay tap; in cascade mode, the FIFO depth
• Step CV input (±5V → ±N): per-lane step modulation, summed with the global N CV input
• Mode switch (horizontal, cascade on left): parallel = N-step delay line on the input; cascade = FIFO fed by the previous lane's value
• DIV knob (÷1, ÷2, ÷3, ÷4, ÷8): clock divider for the lane (slows reads + writes)
• CV out + Gate out + LED

Plus:

• JUMBLE pair — random pick from any of A/B/C/D held values, re-rolled on every input clock; CV out + accompanying CLK trigger out + LED
• Reset button (paired with RESET trigger input)
• Disconnect playback: when CV input is unplugged, lane reads cycle through a 16-slot history ring at clock rate so even cascade-N=1 lanes keep playing through accumulated content
• Right-click → "Clear all" to flush both buffer types + held values + jumble

16HP.

Phase fixes

• Reverse direction now works in rotate mode. Previously the playhead used `std::fabs(speed)` so negative speed never reversed the playback in rotate mode (sleep mode was unaffected). Now signed speed advances in both directions and the playhead wraps at either boundary.
• Recording UI rearranged: gates on the outside, audio inputs in the middle (`GATE A · A IN · B IN · GATE B`). REC A / LINK / REC B buttons aligned over the new positions.
• "Clear A&B" context menu item — wipes both samples in one action and resets the explicit-B flag so the cascade-A-into-B fallback resumes.
• Refreshed Phase panel SVG.

Source

Source-only release. Install via the VCV Library once the build is published, or build from source.