Capability Matrix

Capability Matrix

“Yes” means the current architecture and source contain a usable path. “Limited” calls out an important constraint. Exact availability can depend on the build feature and the connected server.

Capability	Browser-only	Native CPU	Apple MLX	NVIDIA CUDA
Core language and arrays	Yes	Yes	Yes	Yes
Named axes and structured shape errors	Yes	Yes	Yes	Yes
Model DSL	Yes	Yes	Yes	Yes
CPU autograd and optimizers	Yes	Yes	Fallback	Fallback
General arbitrary-model GPU training	No	N/A	Yes	No
Supported LoRA GPU training fast path	No	N/A	Yes	Yes
Supported two-linear MLP GPU training path	No	N/A	Yes	Yes
Tiny/tutorial training	Yes, size-limited	Yes	Mixed by model path	Mixed by model path
Inline visualization	Yes	No, artifact path	Via client/artifact	Via client/artifact
Filesystem load	No	Yes, sandboxed	Yes, native host	Yes, native host
load_preloaded	Yes	Yes	Yes	Yes
Trace export to disk	No	Yes	Yes	Yes
BPE and byte tokenization	Yes	Yes	Yes	Yes
Experiment tracking	Memory	Disk	Disk	Disk
Device feasibility estimation	Yes	Yes	Yes	Yes
Trustworthy calibration	Limited	Yes	Yes	Yes
Direct llm_call or local Ollama	No	Yes	Yes	Yes
Server sessions and inspection	Client only	Server build	Server build	Server build
SSE training telemetry and cancel	Connected client	Yes	Yes	Yes
Session persistence and reattach	Connected client	Yes	Yes	Yes
Compilation to Rust/native	Build elsewhere	Yes, subset	CPU target subset	CPU target subset
Engram conditional memory	Yes, CPU	Yes, CPU	CPU execution	CPU execution

Reading GPU claims correctly

flowchart TD
    Scope[Enter device scope] --> Backend{Backend built and available?}
    Backend -->|No| CPUFallback[Run CPU fallback and warn]
    Backend -->|Yes| Operation{Operation or model shape supported?}
    Operation -->|General forward op| GPUOp[Dispatch GPU operation]
    Operation -->|Recognized training fast path| GPUTrain[Train on GPU]
    Operation -->|Unsupported training graph| Tape[Use CPU autograd tape]
    Tape --> Notice[Do not interpret scope alone as GPU training]

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MLX uses persistent device tensors and a device-aware autograd tape for general training. CUDA accelerates recognized LoRA and two-linear MLP training shapes; other CUDA-scoped training uses the CPU tape. Confirm device telemetry rather than inferring residency from the device scope alone.

See Execution Surfaces for deployment choices and the individual backend pages for build and limitation details.