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@amykyta3 amykyta3 released this 12 Apr 05:27
· 48 commits to main since this release
v1.0.0
833c515

Publishing first "stable" version 1.0! 🎉
Architecture of the regblock generator has stabilized enough that I'm comfortable to start publishing this using proper semantic versions.
Thank you so much to all the early-adopters who helped test, find bugs, and enhance the tool further!

Updates:

  • ⚠️ Drop support for Python 3.6
  • Add simulation-time width assertions to SV interfaces. #128
  • Add user parameters to regblock package. #112
  • Allow for write enable and sticky property. #98
  • Make swmod respect cpuif byte strobes. #137
  • Simplify stickybit implementation for single-bit fields to not create redundant expression. #127
  • Emit error if field that is asynchronously reset uses a dynamic reset value. #129
  • Fix missing error message if multiple unconditional field assignments are inferred. #93
  • Add more specificity to stickybit conditional class
  • Add top-level block size to generated package #134
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