1.3.0

amykyta3 released this 19 Mar 04:00

· 2 commits to main since this release

3f0b765

Updates:

Add support for Wishbone Bus CPU Interface. #196
Refactor readback mux implementation. Improves performance (#155) and eliminates illegal streaming operator usage (#165)

Bugs Fixed:

Fix BLKLOOPINIT Verilator error in axi4-stream cpuif #193
Fix incorrect traversal into externals for read/write buffered regs. #167, #192
Fix incorrect address truncation in OBI interface template. #176
Fix incorrect handling of error response for overlapped registers with read-only and write-only attributes #178
Fixed VSIM-7061 error in test_parity when using latest Questa Simulator. #182

Assets 2