Merge new features to main for hvisor-v0.2 release #193
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…for now, logic needs rewrite
github-actions
bot
added
aarch64
riscv64
loongarch64
feature
KouweiLee
requested changes
Sep 6, 2025
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| pub fn cpuid_to_mpidr_affinity(cpuid: u64) -> (u64, u64, u64, u64) { | ||
| let mpidr = BOARD_MPIDR_MAPPINGS[cpuid as usize]; | ||
| let aff3 = (mpidr >> 32) & 0xff; |
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This may be aff3 = (mpidr >> 24) ?
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According to https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/MPIDR-EL1--Multiprocessor-Affinity-Register, aff3 should be mpidr >> 32
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It is reasonable. All right.
src/device/irqchip/gicv3/mod.rs
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| .position(|&x| x == mpidr) | ||
| .expect("MPIDR from BOARD_MPIDR_MAPPINGS must be present in sorted list"); | ||
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| GIC.get().unwrap().gicr_base + order * PER_GICR_SIZE |
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I have a question here. The correct way to find the gicr base of one cpu is to check if GICR_TYPER.Affinity_value is equal to the mpidr of this cpu. I searched in the internet and found that the order of the cpu's mpidr may not be the order of the cpu's gicr_base.
enkerewpo
reviewed
Sep 6, 2025
src/arch/loongarch64/hypercall.rs
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| use crate::hypercall::HyperCallResult; | ||
| impl<'a> HyperCall<'a> { | ||
| pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult { | ||
| warn!("hv_ivc_info is not implemented for Risc-V"); |
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Risc-V should be LoongArch64 ?
caodg
reviewed
Sep 6, 2025
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we should indicate the current status, the main and new features, in README, and list major changes in CHANGELOG.md
Optimized the structure of GIC parameters.
…mprove logging clarity
This commit deletes the following files from the vendor/fdt/src directory
Refactor: Enhance GICR handling and remove unused FDT code
Update CHANGELOG for version 0.2 with new platform and feature…
KouweiLee
approved these changes
Sep 11, 2025
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