[P0] Another simple test (hand-written)

[tancheng]

Follow fir test:

VectorCGRA/cgra/test/CgraRTL_fir_test.py

Lines 852 to 941 in dc2ba1b

	def sim_fir_return(cmdline_opts, mem_access_is_combinational):
	src_ctrl_pkt = []
	complete_signal_sink_out = []
	src_query_pkt = []
	# kernel specific parameters.
	kStoreAddress = 16 # We no longer need this for storing the result, as we can directly return it to CPU.
	kInputBaseAddress = 0
	kCoefficientBaseAddress = 2
	kSumInitValue = 3
	kLoopLowerBound = 2
	kLoopIncrement = 1
	kLoopUpperBound = 10
	kCtrlCountPerIter = 4
	# Though kTotalCtrlSteps is way more than required loop iteration count,
	# the stored result should still be correct thanks to the grant predicate.
	kTotalCtrlSteps = kCtrlCountPerIter * \
	(kLoopUpperBound - kLoopLowerBound) + \
	10
	kExpectedOutput = 2215
	# Corresponding DFG:
	#
	# 0(phi_const) <---------┐
	# / | \ |
	# 2(+) 4(+) 8(+) |
	# / / / | |
	# 3(ld) 5(ld) 9(cmp) | |
	# \ / | \ | |
	# 6(x) 12(not) 10(grant_predicate)
	# | |
	# ┌--> 7(+) |
	# | / \ |
	# 1(phi_const) 11(grant_predicate)
	# |
	# 13(ret)
	#
	# Corresponding mapping:
	'''
	↑ Y
	(0,5)| 🔳
	(0,4)| .
	(0,3)| .
	(0,2)| .
	(0,1)| 🔳
	(0,0)+-------------→ X
	(1,0)(2,0)(3,0)
	===================================================
	cycle 0:
	[ 🔳 🔳 🔳 🔳 ]
	[ 0(phi_const) → 🔳 🔳 🔳 ]
	↓ ↺
	[ 🔳 🔳 🔳 🔳 ]
	[ 7(+) ───→ 🔳 🔳 🔳 ]
	↺
	---------------------------------------------------
	cycle 1:
	[ 🔳 🔳 🔳 🔳 ]
	[ 2(+ const) 8(+ const) 🔳 🔳 ]
	↺ ↓ ↺
	[ 4(+ const) 🔳 🔳 🔳 ]
	↺
	[ 1(phi_const) 11(grant_pred) 🔳 🔳 ]
	↺ ↺
	---------------------------------------------------
	cycle 2:
	[ 🔳 🔳 🔳 🔳 ]
	[ 3(ld) 🔳 🔳 🔳 ]
	↓ ↑
	[ 5(ld) 9(cmp) 🔳 🔳 ]
	↺ ↺
	[ 🔳 13(ret) 🔳 🔳 ]
	---------------------------------------------------
	cycle 3:
	[ 🔳 🔳 🔳 🔳 ]
	[ 🔳 ← 10(grant_predicate) 🔳 🔳 ]
	[ 6(x) 12(not) 🔳 🔳 ]
	↓ ↓
	[ 🔳 🔳 🔳 🔳 ]
	---------------------------------------------------
	'''

create a CgraRTL_reduce_test.py by hand-writing the control signals based on the mapper generated mapping info: https://github.com/coredac/dataflow/blob/7f845d6a5b9dd3310c237dba5db9934b032f14f4/test/neura/ctrl/branch_for.mlir#L247-L304

This would make you understand the full-stack of the entire framework.

[tancheng]

CCing @n0thingNoob @Jackcuii for viz.

[tancheng]

Hi @ShangkunLi, you can start with the branch_for test in our neura compiler for this issue.

---

@fhgreenery, you can modify the existing test, i.e., replace:

VectorCGRA/cgra/test/CgraRTL_fir_test.py

Line 280 in dc2ba1b

sum += input[i] * coeff[i];

with

output[i] = input[i] * coeff[i];

which is a simple elementwise mul, how does this sound?

---

@zsjiang99, plz make a C++ relu in
https://github.com/coredac/dataflow/blob/7f845d6a5b9dd3310c237dba5db9934b032f14f4/test/neura/for_loop/

like:

   for (i = 0; i < N; ++i) {
     if (input[i] > 0) {
       output[i] += input[i];
     } else {
       output[i] += 0;
     }
   }

for this task.

Plz let me know if anything not clear to you. Thanks~!

[yyan7223]

Have we finished the test now?

[tancheng]

Have we finished the test now?

I am ccing you just to keep you in the loop. Your other tasks have higher priority, but it would be perfect if you can also understand how the kernel/test is programmed.