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Align SP to 16 bytes on AArch64#335

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michalbednarski merged 1 commit into
termux:masterfrom
t184256:aarch64-sp-16-align
Feb 21, 2026
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Align SP to 16 bytes on AArch64#335
michalbednarski merged 1 commit into
termux:masterfrom
t184256:aarch64-sp-16-align

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@t184256 t184256 commented Feb 17, 2026

Originally reported by Michael Hueschen with the following (LLM-generated) description:

On AArch64, SP must be 16-byte aligned. LLVM 17's generated loader code happened to tolerate misaligned SP, but LLVM 21 emits SP-relative addressing in the loader's _start prologue, causing an immediate SIGBUS (BUS_ADRALN) at
PC=0x2000000000 (the loader entry point).

Reported-by: Michael Hueschen <m@mhueschen.space>
petm5 added a commit to petm5/nix-on-droid that referenced this pull request Feb 17, 2026
Temporary until merged upstream

See termux/proot#335
@michalbednarski michalbednarski merged commit ab2e346 into termux:master Feb 21, 2026
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Thanks

As far as I can see, this only affects sp value in loader, not loaded app, so I'm not bumping termux-packages for this Pull Request

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