EQ FIR: Add support for 16 and 24 bit data

[singalsu]

This patch adds to equalizer capability to process 16 and 24 bit
pipelines in addition to 32 bit similarly as IIR. The generic C,
HiFiEP, and HiFi3 versions are updated with the capability.

Signed-off-by: Seppo Ingalsuo seppo.ingalsuo@linux.intel.com

[lgirdwood]

Instead of having all this condition code, can we have a block of conditional code at the start of the file that creates some static inline function to set this mapping for HIFI3 and generic modes. That way we only have one area that is conditionally compiled (and makes it easier to add HIFI2 or HIFI4)

[singalsu]

@lgirdwood I just pushed update for this PR.

[lgirdwood]

sorry, I mean this function will call a

static inline void set_fir_func(cd);

This function will be defined in condition code

#if HIFI3
static inline void set_fir_func(..)
{
}
#elif HIFI2
static inline void set_fir_func()
{
}
#else
/* generic */
static inline void set_fir_func()
{
}
\endif

[singalsu]

I have done a version of this but I can't push it to PR because git master has stopped to work with EQ topology. Need to find a fix for it first.

But just to confirm I did the right thing is it OK to have the 16/24/32 bit format switch-case inside each static inline void set_fir_func()?

[singalsu]

@lgirdwood I just pushed update for this PR with earlier mentioned set_fir_func() style.

I was able to test this but I had to remove earlier commit b5308ee (1k buffers re-introduce + some FIR traces) to avoid DSP panic.

[singalsu]

@lgirdwood @tlauda We suspect memory leak that need to be debugged so better to close this and revert the 1k buffers introduce commit b5308ee.

[singalsu]

Closing.

[singalsu]

Sorry, I closed wrong PR -- reopen.

[singalsu]

Please ignore my comments about memory leak in this thread context. This PR is proposed.

[lgirdwood]

@singalsu can you fix the CI failure and resend

[singalsu]

@lgirdwood This CI issue does not look like EQ related. If the topology doesn't instantiate EQs it only increases a bit the code size. There are similar CI issues for other PRs too.

"ERROR:Exception TimeoutError occurred at 'c:\work\tools\cavs_scripts-py\utilities\fw_loader.py':163 FW not ready after 1.0 seconds!"

[lgirdwood]

Sorry I mean have one switch statement, but have multiple conditionally compiled versions of

static inline void set_s16_fir(struct comp_data *cd)
{
    cd->eq_func_even = blah;
    cd->eq->func = blah;
}

So the single switch just calls the static inline which is conditionally compiled.

static inline int set_fir_func(struct comp_dev *dev)
{
	struct comp_data *cd = comp_get_drvdata(dev);
	struct sof_ipc_comp_config *config = COMP_GET_CONFIG(dev);
 	switch (config->frame_fmt) {
	case SOF_IPC_FRAME_S16_LE:
		trace_eq("f16");
		set_s16_fir(cd);
		break;
	case SOF_IPC_FRAME_S24_4LE:
		trace_eq("f24");
		set_s24_fir(cd);
		break;
	case SOF_IPC_FRAME_S32_LE:

[singalsu]

@lgirdwood I've test pushed a fix a tested this with UP2 with needed PR #464. Sorry for iterations, I hope I got it right this time!

[singalsu]

I just pushed this rebased version with conflict fix.