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[stable-v2.2] intel: ssp: drain RX fifo when starting #7601

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Merged
kv2019i merged 2 commits into from
May 15, 2023
Merged

[stable-v2.2] intel: ssp: drain RX fifo when starting #7601

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ec48d3e
intel: ssp: do not read data directly if DMA is active
kv2019i May 5, 2023
b2b222a
intel: ssp: drain RX fifo when starting
kv2019i May 5, 2023
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22 changes: 19 additions & 3 deletions src/drivers/intel/ssp/ssp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -74,9 +74,18 @@ static void ssp_empty_rx_fifo(struct dai *dai)
uint64_t sample_ticks = clock_ticks_per_sample(PLATFORM_DEFAULT_CLOCK,
ssp->params.fsync_rate);
uint32_t retry = SSP_RX_FLUSH_RETRY_MAX;
bool direct_reads = ssp->state[DAI_DIR_CAPTURE] <= COMP_STATE_PREPARE;
uint32_t entries;
uint32_t i;

#if CONFIG_DMA_SUSPEND_DRAIN
/*
* In drain mode, DMA is stopped before DAI, so flush must be
* always done with direct register read.
*/
direct_reads = true;
#endif

/*
* To make sure all the RX FIFO entries are read out for the flushing,
* we need to wait a minimal SSP port delay after entries are all read,
Expand All @@ -87,9 +96,12 @@ static void ssp_empty_rx_fifo(struct dai *dai)
while ((ssp_read(dai, SSSR) & SSSR_RNE) && retry--) {
entries = SSCR3_RFL_VAL(ssp_read(dai, SSCR3));
dai_dbg(dai, "ssp_empty_rx_fifo(), before flushing, entries %d", entries);
for (i = 0; i < entries + 1; i++)
/* read to try empty fifo */
ssp_read(dai, SSDR);

/* let DMA consume data or read RX FIFO directly */
if (direct_reads) {
for (i = 0; i < entries + 1; i++)
ssp_read(dai, SSDR);
}

/* wait to get valid fifo status and re-check */
wait_delay(sample_ticks);
Expand Down Expand Up @@ -950,6 +962,10 @@ static void ssp_early_start(struct dai *dai, int direction)

key = k_spin_lock(&dai->lock);

/* RX fifo must be cleared before start */
if (direction == DAI_DIR_CAPTURE)
ssp_empty_rx_fifo(dai);

/* request mclk/bclk */
ssp_pre_start(dai);

Expand Down