tplg: add nocodec topology for icelake#26
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| # | ||
| # Define the pipelines | ||
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| # PCM0 ----> volume -----> volume ----> SSP0 |
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typo, I will fix it
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| # BE configurations - overrides config in ACPI if present | ||
| # | ||
| DAI_CONFIG(SSP, 0, 0, NoCodec-0, |
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this looks like all other test topologies, why do you need something specific for ICL?
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some settings are different on different platform. For example, there are 6 SSP ports available on APL, but only 2 on CNL. And MCLK on APL is 19.2MHZ, but on CNL is 24MHZ and on ICL 38.4MHZ. So it makes trouble for others to validate on each platform. So I made this for others to have a easy life
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ok, I didn't click that this the file used by default in nocodec mode, fine.
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| # Low Latency PCM Configuration | ||
| # Low Latency PCM Configuration | ||
| W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) |
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Yes, I will refine it
| # BE configurations - overrides config in ACPI if present | ||
| # | ||
| DAI_CONFIG(SSP, 0, 0, NoCodec-0, | ||
| SSP_CONFIG(DSP_B, SSP_CLOCK(mclk, 38400000, codec_mclk_in), |
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can you check if the MCLK really needs to be that high? Or are we confusing clock source and clock output?
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yes, it is clock source 38.4MHZ on ICL confirmed by AUDIO PEG team.
And I also studied the ssp code, clock output maybe lower, just like 19.2MHZ.
It is just a test at max clock.
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ok for nocodec cases it makes sense to verify the clock output at max rate.
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ok, I get it now, but please fix the word wrap issues in icl.m4
| define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) | ||
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| # Low Latency PCM Configuration | ||
| W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) |
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yes, I will fix it
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Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
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Fix log lines issue |
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Test it on ICL
Signed-off-by: Rander Wang rander.wang@linux.intel.com